Method of designating output “don't care”...

Details Method of designating output “don't care”... Method of designating output “don't care”...

2001-01-16

2003-07-01

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06587993

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of designating an output “don't care” in logic circuit data, an apparatus for doing the same, a processor for carrying out an equivalency test or synthesizing logics, and a method of carrying out an equivalency test or synthesizing logics, and more particularly to such a method, an apparatus and a processor all suitable for effectively carrying out an equivalency test for logic circuit data and effectively producing logic circuit data used for logic synthesis. The invention relates further to a recording medium readable by a computer, storing a program therein for causing a computer to carry out the above-mentioned methods or act as the above-mentioned apparatus or processor.
2. Description of the Related Art
Various methods have been suggested for testing equivalency between two logic circuits. In one of such methods, two logic circuits are converted into logic functions, and those logic functions are judged as to whether they are equivalent to each other.
FIG. 1
is a block diagram of a conventional system for carrying out an equivalency test.
The illustrated system is accomplished by a computer operating in accordance with a program. Specifically, the illustrated system is comprised of a graphic display
1
, a keyboard
2
, a mouse
3
, an external memory
4
, and a tester
101
. The tester
101
is comprised of an input unit
102
including a logic circuit data reader
105
and a data form converter
106
, an equivalency tester
103
, and an internal database
104
.
The logic circuit data reader
105
reader reads both logic circuit data used as reference data in judgment of equivalency with other data and logic circuit data judged as to whether equivalent to the reference data, out of the external memory
4
, and stores the thus read-out logic circuit data into the internal database
104
. Hereinafter, logic circuit data used as reference data in judgment of equivalency with other data is referred to as “reference logic circuit data”, and logic circuit data which is to be judged as to whether it is equivalent to the reference logic circuit data by comparing to the reference logic circuit data is referred to as “tested logic circuit data”. Both the reference and tested logic circuit data are described by HDL which is a language by which a hardware is described, logic formula, a table of truth value, data about gate level connection, and so on.
The reference and tested logic circuit data are read out of the internal database
104
, and are converted by the data form converter
106
into data having a form conforming to an equivalency test carried out by the equivalency tester
103
. The thus converted reference and tested logic circuit data are judged by the equivalency tester
13
as to whether they are logically equivalent to each other.
In a usual case wherein an equivalency test is carried out to gate-leveled
In a usual case wherein an equivalency test is carried out to gate-leveled logic circuit data logically synthesized from register/transfer-leveled original logic circuit data, the register/transfer-leveled original circuit data is used as the reference logic circuit data, and the gate-leveled logic circuit data is tested as to whether it is logically equivalent to the reference logic circuit data by comparing to the register/transfer-leveled original circuit data.
If the reference or tested logic circuit data includes an undefined output “X” among outputs derived therefrom, the equivalency tester
103
judges that the reference and tested logic circuit data are logically equivalent to each other, when the reference logic circuit data outputs an defined value “X”, even if the tested logic circuit data outputs an undefined value “X”, a logical value “0” or a logical value “1”.
On the other hand, when the tested logic circuit data outputs an undefined value “X”, the equivalency tester
103
judges that the reference and tested logic circuit data are logically equivalent to each other, only when the reference logic circuit data outputs an undefined value “X”, but judges that the reference and tested logic circuit data are not logically equivalent to each other, when the reference logic circuit data outputs a value other than an undefined value “X”, such as a logical value “0”.
That is, the reference and tested logic circuit data are judged logically equivalent to each other only when both the reference and tested logic circuit data output a logical value either “0” or “1”.
However, for instance, when the reference and tested logic circuit data are gate-leveled logic circuit data synthesized from register/transfer-leveled original logic circuit data including “don't care” logic, under different conditions, the reference and tested logic circuit data may not be equivalent to each other in an equivalency test.
Herein, “don't care” logic indicates an output which exerts no influence on results of logical operation carried out by subsequent circuits regardless of a value of an output node.
FIG. 2
illustrates an example of synthesizing logic, based on logic circuit data including “don't care” logic.
In
FIG. 2
, logic circuit data
112
of a logic circuit (A) produced by logic synthesis on the basis of original logic circuit data
111
under constraint conditions (A) is used as reference logic circuit data, and logic circuit data
113
of a logic circuit (B) produced by logic synthesis on the basis of original logic circuit data
111
under constraint conditions (B) is tested as to whether the logic circuit data
113
is logically equivalent to the logic circuit data
112
.
In an equivalency test between the logic circuit data
112
and
113
, since an undefined value “X” in the original logic circuit data
111
may be a logical value “0” or “1”, the logic circuit data
112
has to be judged logically equivalent to the logic circuit data
113
. However, since the logic circuit data
112
and
113
are apparently different from each other, the equivalency test system illustrated in
FIG. 1
judges that the logic circuit data
112
and
113
are not equivalent to each other.
In order to avoid such apparent mismatch in logic, caused by “don't care” logic, it is necessary to identify a node having “don't care” logic, and take necessary steps to the thus identified node in order to avoid mismatch in logic.
FIG. 3
is a flow chart of a conventional method of preventing such mismatch in logic, caused by “don't care” logic, and
FIGS. 4A and 4B
illustrate examples of steps carried out for preventing such mismatch in logic.
Hereinbelow, it is assumed that both reference logic circuit data and tested logic circuit data are described in HDL, and HDL in which reference logic circuit data and tested logic circuit data are described are referred to as reference data HDL and tested data HDL, respectively. Hereinbelow are explained steps in the method in
FIG. 3
with reference to
FIGS. 1
,
4
A and
4
B.
With reference to
FIG. 3
, the logic circuit data reader
105
reads the tested data HDL out of the external memory
4
in step
121
. If there is a technology library necessary for mapping a logic circuit described in the tested data HDL, the logic circuit data reader
105
reads the technology library, too.
Then, the logic circuit data reader
105
reads the reference data HDL out of the external memory
4
in the same way as step
121
, in step
122
.
Then, the data form converter
106
converts the tested data HDL into tested circuit data
131
having a form conforming to an equivalency test carried out in the equivalency tester
103
, in step
123
.
Then, the data form converter
106
converts the reference data HDL into reference circuit data
133
having a form conforming to an equivalency test carried out in the equivalency tester
103
, in step
124
.
Then, an operator finds out a node in which “don't care” is established (hereinbelow, such a node is referred to as “don't care node”), in step
125
, and designates a logical value or removes the

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