Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-28
2003-02-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06523153
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a design process of an integrated circuit system, and particularly relates to design technology developed to cope with system-on-chip implementations. More specifically, the present invention pertains to design verification techniques applicable to high level stages of a design process.
An integrated circuit system for an electronic unit has been fabricated until just recently by forming individual types of LSIs such as memories and processors on respective semiconductor chips and then mounting and interconnecting all of these chips together on a motherboard like a printed wiring board.
Over the past few years, however, an integrated circuit system is increasingly required to have its overall size, weight, power dissipation and fabrication cost reduced to further broaden the industrial applicability of an electronic unit including the system. Among other things, a consumer electronic appliance for use in digital information processing has to meet all of these requirements more perfectly than any other electronic unit. Responsive to such a demand from the electronics industry, the prime target of research and development by semiconductor makers is now shifting from memories to system LSIS.
Specifically, a system LSI is a single-chip implementation including memories and various types of logic circuits that are integrated together on a single chip. To realize a “system-on-chip” like this, not only the process technology of forming devices with dissimilar structures on a common substrate, but also the design technology thereof should be greatly innovated.
Thus, according to a suggested technique of designing a system-on-chip, a database is prepared in advance to design so-called “functional blocks” implementing required functions. By using such a database, any desired system LSI can be designed as a combination of these blocks. In such a case, a specific physical structure for executing an intended function has been defined in advance for each functional block. Thus, in the physical design of an overall integrated circuit system, only the interconnections among these functional blocks and peripheral circuits have to be newly defined. In this manner, the conventional method tries to increase the design efficiency considerably.
The conventional design method, however, has the following drawbacks.
At a high level stage of a design process, i.e., at a behavioral level (or algorithm level) stage, a functional block for a system is described as a behavioral model. And at this early stage, the overall design of the system is verified. Next, at a lower level stage of the design process, i.e., at a register transfer level (RTL) stage, the behavioral model for the functional block is mapped to an RTL model, or a physically working model of the functional block. And the RTL model description is verified at this stage. However, if the remaining part of the system still consists of behavioral models, then the overall system is not verifiable yet. That is to say, when behavioral and RTL models, which are associated with mutually different levels of abstraction, coexist in the design data, it is difficult to verify the design of the overall system in a cooperative manner.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to make an overall integrated circuit system being designed verifiable efficiently even if its design data includes models associated with mutually different levels of abstraction.
Specifically, an inventive method of design verification for an integrated circuit system includes the step of making up design data, including RTL and behavioral models in combination, for the system being designed. Each RTL model is described at a register transfer level, while each behavioral model is described at a behavioral level that is an abstraction level higher than the RTL level. The method further includes the steps of: generating an interface model between one of the behavioral models and one of the RTL models that is connected to the behavioral model for the design data; and verifying the design of the system using the design data including the interface model.
In one embodiment of the present invention, the interface model preferably includes a protocol converter for converting a protocol for the behavioral model into a protocol for the RTL model, and vice versa.
In this particular embodiment, the interface model may include a bit precision converter for converting bit precision by means of decimal point representations or bit widths in such a manner that input/output data of the behavioral model matches to input/output data of the RTL model.
Alternatively, the interface model may include a signal converter for matching an input/output signal of the behavioral model to an input/output signal of the RTL model.
As another alternative, the protocol converter may include storage means for storing input/output data of the behavioral model thereon and control means for controlling the storage means.
An inventive method for generating an interface model is applicable to verification of an integrated circuit system that is being designed using design data where RTL and behavioral models coexist. Each RTL model is described at an RTL level, while each behavioral model is described at a behavioral level that is an abstraction level higher than the RTL level. The interface model is generated between one of the behavioral models and one of the RTL models that is connected to the behavioral model.
In one embodiment of the present invention, the interface model preferably includes a protocol converter for converting a protocol for the behavioral model into a protocol for the RTL model, and vice versa.
In this particular embodiment, the interface model may include a bit precision converter for converting bit precision by means of decimal point representations or bit widths in such a manner that input/output data of the behavioral model matches to input/output data of the RTL model.
Alternatively, the interface model may include a signal converter for matching an input/output signal of the behavioral model to an input/output signal of the RTL model.
As another alternative, the protocol converter may include storage means for storing input/output data of the behavioral model thereon and control means for controlling the storage means.
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Mizuno Masanobu
Takemura Kazuyoshi
Siek Vuthe
Tat Binh
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