Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-03-04
2001-02-06
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06185721
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of design for testability for integrated circuits (LSIs).
A typical example of the conventional method of design for testability includes a scan path method. In the scan path method, a flip-flop (FF) included in a logically designed LSI is replaced with a scan FF which can be externally directly controlled (scanned in) and observed (scanned out), so that a problem of a sequential circuit can be simplified into a problem of a combinational circuit. Thus, a test sequence can be easily generated (“Digital Systems Testing and Testable DESIGN, Chapter 9, Design For Testability”, 1990, published by Computer Science Press).
However, such a conventional method of design for testability has the following problems:
(1) Since an FF is replaced with a scan FF, the LSI is increased in area.
(2) Since a test input pattern for the scan-in/out operation on a scan chain is required, the number of test input patterns is increased, resulting in increasing time required for the test of the LSI.
(3) Since an FF is replaced with a scan FF after logical design, it is necessary to examine the operation timing of the LSI again. According to circumstances, the LSI is required to be logically designed again, namely, so-called the re-design of the LSI is required. This elongates time for designing the LSI.
SUMMARY OF THE INVENTION
The object of the invention is providing a method of design for testability in which an integrated circuit is modified in design at a register transfer level (RTL; i.e., a level of functional design) with high abstraction than a gate level (i.e., a level of logical design), so as to be simply testable, and in which an area of a test circuit and the number of test patterns can be decreased as compared with those in the conventional method.
Specifically, the method of design for testability at a register transfer level of this invention comprises a partitioning step for partitioning an RTL circuit, which is an integrated circuit designed at the register transfer level, into blocks each satisfying a previously defined simply testable condition, thereby simplifying a test conducted after manufacture.
Furthermore, the method of design for testability at a register transfer level of this invention further comprises an isolation step for modifying design of the RTL circuit, which has been partitioned into the blocks each satisfying the simply testable condition, thereby making the blocks independently testable.
Accordingly, the RTL circuit is first partitioned into the blocks each satisfying the simply testable condition in the partitioning step, and then in the isolation step, the design is modified so that the respective blocks can be independently singly tested. As a result, the RTL circuit can be tested in each of the blocks with a difficulty in generating a test sequence substantially the same as that of the scan path method. Therefore, there is no need to replace an FF with a scan FF after the logical design. This can decrease the area of the LSI (RTL circuit) and the number of test sequences required for the test thereof as compared with those in the conventional method.
In addition, there is no need of re-design, and hence there is no need to conduct the logical design again because the test simplifying design is effected at the RTL, which can decrease time required for designing the LSI as compared with time required in the conventional method.
In one aspect, the simply testable condition is preferably that a circuit in the block has an acyclic structure including no feedback loop.
In another aspect, the simply testable condition is preferably that a circuit in the block has an n-fold line-up structure in which signal paths between an arbitrary register and an arbitrary external output or pseudo-external output have n sorts or less of sequential depths, wherein n is a positive integer.
In still another aspect, the partitioning step preferably includes a first process for selecting, among functional facilities included in the RTL circuit, one functional facility which belongs to none of the blocks, and for generating one block including the selected functional facility; a second process for selecting another functional facility, which is adjacent to the block generated in the first process and does not belong to any other blocks, and for inserting the selected functional facility into the generated block; and a third process for discriminating whether or not the generated block is simply testable in accordance with the previously defined simply testable condition, and when the generated block is discriminated to be not simply testable, for removing the functional facility inserted in the second process from the generated block.
In still another aspect, the partitioning step preferably further includes a fourth process for removing, from the generated block, the functional facility inserted into the generated block in the second process in a reverse order to an inserting order so as to make an input number of the generated block smaller than an input number of the RTL circuit and an output number of the generated block smaller than an output number of the RTL circuit
In still another aspect, the partitioning step preferably includes a process for identifying a register having a self-loop and a finite state machine included in the RTL circuit as a scan register.
In still another aspect, the partitioning step preferably includes a process for obtaining relationship in reachableness between each input and each output of the block by extracting an input reachable to each output, and obtaining a plurality of inputs of the block whose value is controllable through a common external input pin of the RTL circuit on the basis of the relationship.
In still another aspect, the partitioning step preferably includes, when any of the functional facilities has a larger input number or larger output number than the RTL circuit, a process for converting the functional facility into an equivalent circuit including functional facilities each having a smaller input number and a smaller output number than the RTL circuit.
In still another aspect, the partitioning step preferably includes a process for collecting finite state machines included in the RTL circuit in a common block.
Furthermore, the isolation step preferably includes a first process for generating, in the RTL circuit which has been partitioned into the blocks each satisfying the simply testable condition, an input controlling multiplexer for making an input of each block externally directly controllable and an output observing multiplexer for making an output of each block externally directly observable; and a second process for generating, in the RTL circuit in which the input controlling multiplexer and the output observing multiplexer have been generated in the first process, an isolation controller including a finite state machine for controlling the output observing multiplexer for making the blocks successively testable and a decoder for decoding a content of a register included in the finite state machine.
In still another aspect, the partitioning step preferably further includes a process, in partitioning the RTL circuit into the blocks, for identifying a register having a self-loop included in the RTL circuit as a scan register, and the isolation step preferably further includes a third process for replacing the register having been identified as a scan register in the process of the partitioning step with a scan register and for forming scan chains by connecting the scan register in each of the blocks; and a fourth process for generating a multiplexer, using scan-out data of the scan chains formed in the third process as an input, for selecting and outputting one of scan-out data of the scan chains.
In still another aspect, the isolation step preferably includes a process for forming, in the RTL circuit having been partitioned into the blocks each satisfying the simply testable condition, a scan chain in each of the blocks, thereby making an input signal
Do Thuan
Lintz Paul R.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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