Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
1999-03-05
2001-05-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S243000
Reexamination Certificate
active
06232196
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to depositing silicon, and particularly to the chemical vapor deposition of conductively doped silicon with high step coverage.
BACKGROUND OF THE INVENTION
As a semiconducting material, silicon is currently the most popular material from which to fabricate transistors in integrated circuits. Through selective doping of different areas on a silicon substrate, source, drain and channel regions of different conductivity types and levels can be formed in the silicon substrate. Typically, the substrate comprises a monocrystalline silicon wafer, or an epitaxial silicon layer formed thereon. Either the entire substrate (wafer or epitaxial layer) or a region known as a “well” is provided with a relatively low level of background doping of a first conductivity type (e.g., p-type). Source and drain regions can then be defined within that region by heavily doping with dopants of an opposite conductivity type (e.g., n-type source/drain regions within p-wells). Sub-regions are often also formed within the transistor area, with different levels, grading and types of dopants, in order to tailor the electrical characteristics of the resulting electronic devices.
Because silicon most often forms or is part of the base semiconducting layer in which transistors are formed, silicon is also often used in the fabrication of associated circuit elements. Particularly where the circuit element makes direct contact with the silicon substrate, silicon is a preferred material since it is electrically compatible with and forms ohmic contact with the substrate. Many metal materials, in contrast, can poison or interfere with the electrical characteristics of active areas. Other advantages of silicon, such as its high melting point and, therefore, ability to withstand later high-energy steps such as glass reflow or dopant implantation, favor use of silicon for still other applications.
Accordingly, silicon is often used for formation of transistor gate electrodes, capacitor electrodes, metal-to-substrate contacts, conductive plugs between wiring layers, etc. Unfortunately, many of these applications require coverage of steep steps in the topography of the in-process integrated circuit. For example, capacitors are often formed in trenches within the silicon substrate (trench capacitors) or in integrated structures above the substrate (stacked capacitors). Contact plugs, whether they are formed between two wiring layers or from one wiring layer to the substrate, are formed within holes etched through an insulating layer.
In each of these applications, the aspect ratio (height:width) of the structure continues to increase as device density is increased in pursuit of ever-faster and smaller integrated circuits. In general, the higher the aspect ratio, the more difficult it is to evenly cover vertical side walls and the bottom of the contact opening, via, or trench structure at issue. Completely filling such structures is even more difficult. Deposited layers tend to build more quickly at the lip of openings, closing off the opening before the hole is filled. This results in voids or keyholes within the hole.
Polycrystalline silicon (polysilicon, or simply poly) can be deposited by chemical vapor deposition (CVD). CVD silicon is favored over physical vapor deposition (PVD) of conductive materials, such as most metals, for its step coverage into high aspect ratio holes. On the other hand, silicon must be doped for conductivity and ohmic contact, which adds to the expense of forming silicon layers. Such expense is particularly high where the doping is conducted after formation of the silicon layer, such as through implantation or diffusion. Post-formation doping increases costs through a reduction of throughput due to the additional step or steps required for the doping. Additional costs are imposed by the need to protect other existing structures from high-energy dopant implantation or from high-temperature prolonged diffusion steps. Moreover, it is often technically difficult to adequately dope deep silicon plugs, for example, after the structure has been formed.
While processes for in situ doping silicon layers (that is, adding dopants during deposition of the silicon) are known, in situ doping is generally impractical for applications requiring high step coverage. It has been found that the addition of dopant gases to the reactants in CVD of silicon tends to reduce step coverage. Lowering the deposition rate can help in improving step coverage, for instance by lowering the temperature and/or pressure during the deposition, as a general proposition. Even such improvements in step coverage, however, are inadequate for covering or filling high aspect ratio holes of current and future generation integrated circuits. Furthermore, the reduction in throughput caused by lowering deposition rates makes this option unattractive, particularly where additional doping steps will be required after the deposition.
Accordingly, a need exists for a process for depositing silicon into holes or trenches having high aspect ratios with good step coverage and at acceptable rates of deposition. Desirably, such processes should permit in situ doping of the silicon, to avoid the need for further doping steps.
SUMMARY OF THE INVENTION
Methods are disclosed herein for depositing amorphous and/or polycrystalline silicon layers at high pressures. Advantageously, high step coverage can be obtained in holes of high aspect ratios, while maintaining temperatures high enough to achieve commercially acceptable rates of deposition.
In the illustrated embodiment, silane and hydrogen flow in a single-wafer process chamber under atmospheric pressure. At temperatures of 650° C., for example, deposition rates higher than 50 nm/min can be achieved with in situ doping, and higher than about 100 nm/min for undoped silicon. Such high deposition rates are achievable even while filling extremely high aspect ratio vias with excellent step coverage. For example, capacitor trenches having widths of 0.25 &mgr;m and depths of 7 to 7.5 &mgr;m were filled without voids with polysilicon by the methods disclosed herein.
In accordance with one aspect of the invention, therefore, methods are provided for depositing silicon at greater than about 500 Torr chamber pressure, while flowing process gases with a residence time of less than about 100 seconds.
In accordance with another aspect of the invention, a process is provided for depositing a non-epitaxial silicon layer by chemical vapor deposition. A substrate is placed into a single-wafer processing reaction chamber. The substrate temperature is raised to a reaction temperature between about 625° C. and 850° C., and process gases including a silicon source gas and a hydrogen carrier gas are introduced to the reaction chamber. The process gases flow over the substrate while the reaction chamber is maintained at a pressure of greater than about 700 Torr.
In accordance with another aspect of the invention, a method is provided for depositing silicon by chemical vapor deposition. A semiconductor substrate, including a plurality of holes, is loaded into a reaction chamber. The holes have openings of no more than about 0.5 &mgr;m and aspect ratios of greater than about 2:1. The substrate temperature is ramped to a desired reaction temperature. The chamber pressure pressure is maintained at greater than about 700 Torr, and a silane-based silicon source gas, a hydrogen carrier gas, and a dopant source gas flow simultaneously over the substrate within the reaction chamber at the desired reaction temperature. An in situ conductively doped silicon layer is thereby deposited over the substrate and into the holes, exhibiting greater than about 70% step coverage of the holes.
In accordance with another aspect of the invention, a method is disclosed for forming an integrated circuit. A substrate is provided with a hole having greater than a 2:1 aspect ratio. The substrate is loaded into a single-wafer processing chamber, and silicon is deposited into the hole at a rate
Grassl Andreas
Gschwandtner Alexander
Pomarède Christopher François Lilian
Raaijmakers Ivo
van der Jengd Cornelius Alexander
ASM America Inc.
Hoang Quoc
Knobbe Martens Olson & Bear LLP
Nelms David
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