Method of depositing silicon oxides

Details Method of depositing silicon oxides Method of depositing silicon oxides

1999-09-30

2002-04-16

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S632000, C438S659000, C438S766000, C438S782000, C438S781000

Reexamination Certificate

active

06372669

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of depositing silicon oxides, such as silicon dioxide, over substrates.
BACKGROUND OF THE INVENTION
In methods of forming integrated circuits, it is frequently desired to isolate components of the integrated circuits from one another with insulative material. Such insulative material may comprise a number of materials, including for, example, silicon dioxide, silicon nitride, and undoped semiconductive material. Although such materials have acceptable insulative properties in many applications, the materials disadvantageously have high dielectric constants which can lead to capacitive coupling between proximate conductive elements. For instance, silicon dioxide has a dielectric constant of about 4, silicon nitride has a dielectric constant of about 8, and undoped silicon has a dielectric constant of about 12. As circuit density increases with device geometries becoming smaller, the associated RC delay time increases, and hence there is a need to reduce capacitance below that of silicon dioxide material. Further as geometries have become smaller, it is much more difficult to conformally deposit layers into contact and other openings having high aspect ratio.
One known way of achieving desired lower dielectric constant silicon oxides, such as silicon dioxide, is to provide suitable dopant atoms within the material. Fluorine is but one example, to provide a fluorinated silicon oxide of the general formula F
x
SiO
y
.
One recently developed technique for achieving suitable deposition into substrates having high aspect ratio topography, has been developed by Electrotech Limited of Bristol, U.K., and is referred to as a Flowfill™ technology. In such process, SiH
4
and H
2
O
2
are separately introduced into a CVD chamber, such as a parallel plate reaction chamber. The reaction rate between SiH
4
and H
2
O
2
can be moderated by the introduction of nitrogen into the reaction chamber. The wafer is ideally maintained at a suitably low temperature, such as 0° C. at an exemplary pressure of
1
Torr to achieve formation of a silanol-type structure of the formula Si(OH)
4
which condenses onto the wafer surface. Although the reaction occurs in the gas phase, the deposited Si(OH)
4
is in the form of a very viscous liquid which flows to fill very small gaps on the wafer surface. And as deposition thickness increases, surface tension drives the deposited layer flat, thus forming a planarized layer over the substrate.
The liquid Si(OH)
4
is typically then converted to a silicon dioxide structure by a two-step process. First, polymerization of the liquid film is promoted by increasing the temperature to about 100° C. to result in solidification and formation of a polymer layer. Thereafter, the temperature is raised to approximately 450° C. to depolymerize the substance and form SiO
2
. The depolymerization temperature also provides the advantage of driving undesired water from the resultant SiO
2
layer.
Doping of such SiO
2
layer has in the past been attempted by providing a dopant gas in combination with the gaseous H
2
O
2
and gaseous SiH
4
precursors during the initial formation of the Si(OH)
4
liquid. Such deposition techniques have not met with much success and few if any suitable chemistries have been discovered for such to date. Most attempts for dopant incorporation in this manner invariably result in the loss of the desired flow-filling properties of the films.
Accordingly, it would be desirable to develop alternate methods of achieving doped silicon oxides, such as silicon dioxides, formed via a process using silicon oxide precursors, such as for example Si(OH)
4
.
SUMMARY OF INVENTION
The invention comprises methods of depositing silicon oxide material onto a substrate. In but one aspect of the invention, a method of depositing a silicon oxide containing layer on a substrate includes initially forming a layer comprising liquid silicon oxide precursor onto a substrate. After forming the layer, the layer is doped and transformed into a solid doped silicon oxide containing layer on the substrate. In a preferred implementation, the doping is by gas phase doping and the liquid precursor comprises Si(OH)
4
. In the preferred implementation, the transformation occurs by raising the temperature of the deposited liquid precursor to a first elevated temperature and polymerizing the deposited liquid precursor on the substrate. The temperature is continued to be raised to a second elevated temperature higher than the first elevated temperature and a solid doped silicon oxide containing layer is formed on the substrate.


REFERENCES:
patent: 4675716 (1987-06-01), Jones
patent: 5192697 (1993-03-01), Leong
patent: 5457073 (1995-10-01), Ouellet
patent: 5527561 (1996-06-01), Dobson
patent: 5531183 (1996-07-01), Sivaramakrishnam et al.
patent: 5569624 (1996-10-01), Weiner
patent: 5670397 (1997-09-01), Chang et al.
patent: 5700720 (1997-12-01), Hashimoto
patent: 5703404 (1997-12-01), Matsuura
patent: 5811849 (1998-09-01), Matsuura
Ghandhi, VLSI Fabrication Principles silicon and gallium arsenide, 337-339, 1983.*
Wolf, Silicon processing for the VLSI era, pp. 308-311, 1986.*
McClatchie, S., et al., “Low Dielectric Constant FLOWFILL® Technology For IMD Applications”.
Electrotech Ltd., Bristol, U.K., pp. 1-7, no date.
Kiermasz, A., et al., “Planarisation For Sub-Micron Devices Utilising A New Chemistry”.
Electrotech Ltd., UK., pp. 1-3, DUMIC Conference, California (Feb./1995).
Beekmann, K., et al., “Sub-Micron Gap Fill and In-Situ Planarisation Using FLOWFILL® Technology”.
Electrotech Ltd., U.K., pp. 1-7, VLSI Conference, Portland, Oregon (Oct./1995).
Ghandhi, VLSI Fabrication Principles silicon and gallium arsenide, 337-339, 1983.

Affiliated with

Also associated with

Rating

Method of depositing silicon oxides does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of depositing silicon oxides, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of depositing silicon oxides will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2933366