Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-01
2001-03-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S778000, C438S779000, C438S787000
Reexamination Certificate
active
06197677
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of depositing a silicon oxide layer on a semiconductor wafer, and more particularly, to a method of depositing a silicon oxide layer on the transistors and other areas over the surface of the semiconductor wafer.
2. Description of the Prior Art
In semiconductor processing, some gases such as silane (SiH
4
), tetra-ethyl-ortho-silicate (TEOS) and oxygen are used in a thin film deposition process to form a dielectric layer. The chemical reaction between the gases forms a thin film on the semiconductor wafer to provide electrical insulation between devices. Because the manufacturing technology of silicon oxide (SiO
x
) is very well developed, a silicon oxide (SiO
x
) layer is most frequently used as the dielectric layer in most semiconductor wafer processes. Atmospheric pressure chemical vapor deposition (APCVD) is usually employed in the prior art method. O
3
and TEOS are used as reactive gases to form the silicon oxide layer. This method is abbreviated as O
3
-TEOS in the semiconductor industry. The silicon oxide layer formed by this method has good gap filling ability, so it is usually used in the inter-metal layer or inter-layer dielectric.
Please refer to FIG.
1
.
FIG. 1
is a sectional schematic diagram of silicon oxide layer
19
deposited on semiconductor wafer
11
according to the prior art. In the prior art method of forming silicon oxide layer
19
, semiconductor wafer
11
is loaded on an APCVD machine to undergo an APCVD process by using the O
3
-TEOS method. Silicon oxide layer
19
will then be formed on semiconductor wafer
11
. The surfaces of each transistor on semiconductor wafer
11
are usually formed by many different materials, as shown in FIG.
1
. The surface of semiconductor wafer
11
comprises silicon oxide layer
12
and polysilicon
13
which is filled inside silicon oxide layer
12
. The deposition layer
19
on semiconductor wafer
11
and transistors is formed by gases mixed with TEOS and a predetermined amount of highly concentrated ozone.
However, highly concentrated ozone is very sensitive to the surfaces formed by different materials on the semiconductor wafer
10
. The relative deposition rates of each material are as follows: Si >SiN>SiO
2
formed by a thermal oxidation process >SiO
2
formed by a deposition process. Consequently, the deposition rate of deposition layer
19
formed on the surface of the semiconductor wafer
11
will vary with the different surface materials. Hence, if highly concentrated ozone is used to perform the deposition process, silicon oxide layer
19
will form on semiconductor wafer
11
with uneven thicknesses, that will reduce the manufacturing yield.
Therefore, for solving the above problem caused by employing highly concentrated ozone as the reactive gas in the deposition process, the semiconductor industry usually creates a buffer layer on the semiconductor wafer first, in order to reduce the sensitivity of highly concentrated ozone. Please refer to FIG.
2
.
FIG. 2
is a sectional schematic diagram of silicon oxide layer
17
deposited on the semiconductor wafer
10
according to the prior art. The semiconductor wafer
10
comprises a plurality of transistors
12
positioned on its surface, wherein the transistors consist of Si, SiO
2
and SiN. In the prior art method, TEOS and a low concentration of ozone are injected to form the first silicon oxide layer
14
as a buffer layer on the semiconductor wafer
10
. Then TEOS and highly concentrated ozone are injected to form the second silicon oxide layer
16
on the semiconductor wafer
10
. The silicon oxide layer
17
consists, then, of the first silicon oxide layer
14
and the second silicon oxide layer
16
, and is used as the dielectric layer.
For the silicon oxide layer
17
shown in
FIG. 2
, TEOS and a low concentration of ozone are injected as the reactive gases. Because a low concentration of ozone also has a low sensitivity characteristic, the first silicon oxide layer
14
will be formed on the semiconductor wafer
10
with a thin thickness. Then highly concentrated ozone and TEOS are injected to form the second silicon oxide layer
16
with a thick thickness and a uniform surface over the first silicon oxide layer
14
. Because the second silicon oxide layer
16
is deposited on the surface of the first silicon oxide layer
14
, which is a single material, the sensitivity of highly concentrated ozone to the semiconductor wafer
10
is uniform. Consequently, the second silicon oxide layer
16
forms as a flat surface.
However, the gap filling ability of the first silicon oxide layer
14
is very poor. Voids
18
are easily formed in trenches, or in places between devices during the deposition process. These defects can result in short circuits and reduce the reliability of the transistors on the semiconductor wafer
10
, which increases production costs. Moreover, as the manufacturing technology improves, the design of line widths and line distances on the semiconductor wafer
10
decrease. The poor gap filling ability of the first silicon oxide layer
14
formed by the prior art method will cause more voids
18
on the semiconductor wafer
10
during the manufacturing process and will immensely effect the electrical performance of the semiconductor wafer
10
.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of depositing a silicon oxide layer to solve the above mentioned problem.
In a preferred embodiment, the present invention provides a method of depositing a silicon oxide layer on a semiconductor wafer, the semiconductor wafer comprising a plurality of transistors positioned on its surface, the method comprising:
performing a cleaning process to the semiconductor wafer by using an alkaline solution; and
performing a deposition process by employing ozone as a reactive gas to form a silicon oxide layer on the semiconductor wafer;
wherein the cleaning process performed on the semiconductor wafer with the alkaline solution causes the deposition rate of the silicon oxide layer on the transistors and other areas over the surface of the semiconductor wafer to be more uniform.
It is an advantage of the present invention that the method of depositing a silicon oxide layer can improve the gap filling ability of the silicon oxide layer to prevent voids that can cause short circuits.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5210056 (1993-05-01), Pong et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5933760 (1999-08-01), Iyer et al.
patent: 5943599 (1999-08-01), Yao et al.
patent: 6004886 (1999-12-01), Houng et al.
Lee Chin-Hui
Lin Ting-Chi
Liu Chih-Cheng
Hsu Winston
Smith Matthew
United Microelectronics Corp.
Yevsikov V.
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