Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-12
2005-04-12
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S019000
Reexamination Certificate
active
06880142
ABSTRACT:
A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.
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Bhutani Sandeep
Corbeil, Jr. John D.
Cui Qian
Davis Robert W.
Krishnamurthy Prabhakaran
Garbowski Leigh M.
LSI Logic Corporation
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