Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2001-06-08
2004-05-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S764000, C714S773000, C365S200000, C365S201000
Reexamination Certificate
active
06735726
ABSTRACT:
BACKGROUND
In general, the present invention relates to a method of determining an error rate and a semiconductor integrated circuit device. More particularly, the present invention relates to an effective technology such as a data holding technology adopted in a memory circuit comprising dynamic memory cells.
As a result of a survey conducted after the present invention, Unexamined Patent Publication No. Hei 11(1999)-213659 and Unexamined Patent Publication No. Hei 7(1995)-262794 were identified. Referred to hereafter as prior art 1 and prior art 2 respectively, the former and latter publications are considered to be relevant to the present invention described later in this specification. Prior art 1 is a technology to control the frequency of refresh cycles by a CPU through execution of software using the number of erroneous rows detected by an error correction compound circuit in order to optimize intervals of refresh cycles of a DRAM in a sleep state. On the other hand, prior art 2 is a technology of detecting an error by means of an ECC circuit embedded in a DRAM and writing correction data into a memory cell.
SUMMARY OF THE INVENTION
However, descriptions of prior art 1 and prior art 2 do not include a suggestion to optimize an information holding time of each memory cell by monitoring an error rate at refresh cycles with a high degree of precision as is the case with the present invention to be described later.
There is no sufficient study of how to form a judgment on an erroneous row count detected by the error correction compound circuit to be used in controlling the frequency of refresh cycles as is the case with prior art 1. For example, let the refresh period be shortened immediately after the number of erroneous rows reaches an allowable limit in the course of a refresh operation. Assume that the number of erroneous rows disappears in a refresh operation of memory cells, which is carried out later. In this case, it is impossible to determine whether the number of erroneous rows disappears as a result of the shortening of the refresh period or the number of erroneous rows disappears due to the fact that the number of erroneous rows is concentrated at the beginning of a refresh operation. In other words, an erroneous row may possibly disappear in some cases even if the refresh period is not shortened as described above. If the refresh period is changed in the course of a refresh operation as described above, a result of error detection carried out on memory cells later on will be ignored. Thus, the memory cells' power to sustain data is not determined correctly.
In order to solve the problem described above, there is conceived a technique whereby the number of erroneous rows is compared with the allowable limit after the refresh operation is completed for all memory cells. If the number of erroneous rows is compared with the allowable limit after the refresh operation is completed for all memory cells, however, a problem caused by an erroneous row count far exceeding the allowable limit after the refresh operation can no longer be solved. As a result, the expected reliability of the error correction cannot be assured anymore.
In addition, prior art 2 does not include a concept of controlling the frequency of refresh cycles by using the number of erroneous rows detected by an error correction compound circuit.
From a standpoint of power consumption reduction which is the original objective, in prior art 1, a question remains to be answered. To be more specific, the problem to be further studied is control of the frequency of refresh cycles using the number of erroneous rows detected by an error correction compound circuit. Such control is mainly implemented by execution of software by a central processing unit. In this configuration, in order to just sustain data stored in a DRAM, the CPU intervenes by generating an address and reads out as well as writes data from and into the address in the DRAM for a refresh cycle of the DRAM. Thus, the DRAM consumes a large power for outputting data to a system bus having a relatively large load-bearing capacity. In addition, a large power is also consumed by the CPU for driving an address bus having a large load-bearing capacity as well in an operation to output an address to the DRAM. Thus, in comparison with power consumption in the conventional self-refresh operation wherein only an internal circuit of the row system operates as driven by the DRAM itself, it is hardly thinkable that reduction of the frequency of refresh cycles using the number of erroneous rows detected by an error correction compound circuit is beneficial for a system including a DRAM mounted thereon.
It is thus an object of the present invention addressing the problems described above to provide a method of determining a data error rate with a high degree of reliability and to provide a semiconductor integrated circuit device having reduced power consumption for an operation to sustain information while assuring high reliability of a memory circuit comprising dynamic memory cells.
The above and other objects as well as novel features of the present invention will become more apparent from a careful study of the specification with reference to accompanying diagrams.
An outline of a representative of inventions disclosed in this specification is explained briefly as follows. An error rate of a plurality of pieces of data is determined by executing the steps of:
detecting an error in the pieces of data by using the pieces of data and additional inspection bits generated for the pieces of data;
accumulating first detection signals each indicating non-existence of an error to produce a total;
multiplying a second detection signal indicating existence of an error by a weight predetermined for an error rate to produce a product greater than each of the first detection signals; and
subtracting the product from the total.
An outline of another representative of inventions disclosed in this specification is explained briefly as follows. A memory circuit comprising dynamic memory cells and having an information sustaining mode includes:
an ECC circuit activated in the information sustaining mode of the memory circuit in order to detect and correct an error by executing the steps of:
reading out a plurality of pieces of data stored in the memory circuit;
generating inspection bits for detecting and correcting an error in the pieces of data;
storing the inspection bits in an additional memory circuit; and
reading out back the pieces of data and the inspection bits associated with the pieces of data in a predetermined refresh period, and
an error rate select circuit for setting a refresh period by executing the steps of:
accumulating first detection signals each indicating non-existence of an error detected by the ECC circuit in a first direction to produce a total;
accumulating second detection signals each indicating existence of an error detected by the ECC circuit in a second direction to subtract a quantity from the total where the quantity is a product of the second detection signal and a weight and greater than each of the first detection signals; and
increasing a refresh cycle by a predetermined time length for the total's value exceeding a predetermined width in the first direction or decreasing the refresh cycle by a predetermined time length for the total's value exceeding a predetermined width in the second direction.
REFERENCES:
patent: 4758992 (1988-07-01), Taguchi
patent: 4794597 (1988-12-01), Ooba et al.
patent: 6065146 (2000-05-01), Bosshart
patent: 6236602 (2001-05-01), Patti
patent: 6560725 (2003-05-01), Longwell et al.
patent: 7-262794 (1995-10-01), None
patent: 11007760 (1999-01-01), None
patent: 11-213659 (1999-08-01), None
Mano, T.; Yamada, J.; Inoue, J.; Nakajima, S.; Circuit techniques for a VLSI memory, IEEE Journal of Solid-State Circuits, vol.: 18 Issue: 5, Oct 1983, pp.: 463-470.
Ito Yutaka
Kato Hideaki
Muranaka Masaya
De'cady Albert
Miles & Stockbridge P.C.
Torres Joseph D.
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