Method of debugging in a computer system

Details Method of debugging in a computer system Method of debugging in a computer system

1996-10-17

2000-08-01

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 38, G06F 1100

Patent

active

060981830

ABSTRACT:
In a computer system which has a system memory, an integrated circuit socket that is normally used for mounting a BIOS memory thereon, an input/output port, and a central processing unit connected to the system memory, the integrated circuit socket and the input/output port, a method of debugging in the computer system includes mounting a debugging memory which is programmed with a debugging routine on the integrated circuit socket, connecting an external computer terminal to the input/output port, and activating the computer system such that the central processing unit executes the debugging routine and such that the central processing unit is capable of downloading and executing software instruction codes from the external computer terminal.

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patent: 4837764 (1989-06-01), Russello
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patent: 5581695 (1996-12-01), Knoke et al.
patent: 5615331 (1997-03-01), Toorians et al.
patent: 5630048 (1997-05-01), La Joie et al.
patent: 5640542 (1997-06-01), Whitsel et al.
patent: 5680620 (1997-10-01), Ross

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