Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-11-08
2001-10-02
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S156000, C438S160000, C438S162000, C257S055000
Reexamination Certificate
active
06297080
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of Invention
The present invention relates to a method of crystallizing a silicon film and a method of manufacturing a liquid crystal display apparatus which uses the Joule heat of a heat generating conductive layer to increase the temperature of a silicon film for expediting silicon crystallization.
II. Discussion of Related Art
An active layer of a thin film transistor (hereinafter abbreviated TFT) in a liquid crystal display (hereinafter abbreviated LCD) is made of a silicon film which is in a polycrystalline state because the mobility of electric charges of polycrystalline silicon is higher than that of amorphous silicon. Polycrystalline silicon has usually been formed at a high temperature. A new technique of manufacturing a TFT of polycrystalline silicon at low temperature is currently being used.
Low temperature polycrystalline silicon has various advantages such as the low process temperature, the capability of forming a large LCD area and the comparability of performance equal to the high temperature polycrystalline silicon process. There are several methods of forming low temperature polycrystalline silicon such as Solid Phase Crystallization (hereinafter abbreviated SPC), Laser Crystallization and other methods.
Laser crystallization crystallizes amorphous silicon into polycrystalline silicon by applying a laser to an amorphous silicon layer under 400 degrees Celsius and provides excellent performance. Unfortunately, the crystallization fails to provide uniformity. The method is not suitable for manufacturing polycrystalline silicon for a large scale LCD due to the high cost of equipment and low productivity.
SPC crystallizes amorphous silicon into the polycrystalline silicon (polysilicon) by carrying out heat treatment at 550 to 700 degrees Celsius for about 24 hours and provides uniform polycrystals using equipment that is not so expensive. Unfortunately, the temperature and time required for crystallization are high and long so that a glass substrate cannot be used. Also, productivity using this method is low.
Another technique for the crystallization of amorphous silicon is Metal Induced Crystallization (hereinafter abbreviated MIC) which is illustrated in FIG.
1
A and FIG.
1
B. MIC achieves crystallization by contacting amorphous silicon with a metal catalyst which accelerates the silicon crystallization at about 500 degrees Celsius.
Referring to
FIG. 1A
, after a buffer layer
10
of silicon oxide has been formed on an insulated substrate
100
, an amorphous silicon layer
11
is deposited on the buffer layer
10
. Then, a metal film
13
such as a Ni film working as a catalyst layer for crystallization is formed on the amorphous silicon layer
11
. In this case, the metal film
13
of Ni is deposited on the amorphous silicon layer
11
by sputtering which is a conventional method of depositing metal.
Referring to
FIG. 1B
, the amorphous silicon layer
11
undergoes heat treatment on the above substrate for crystallization.
As a result of the heat treatment, silicide (not shown) is formed by diffusion of the Ni layer toward a silicon layer so as to form a silicide region at the boundary of the silicon layer and Ni layer. The silicide accelerates the crystallization of the silicon film to crystallize the amorphous silicon layer into a polycrystalline film
19
at a low crystallization temperature.
In MIC as a related art, silicon crystallization occurs by forming a Ni film having a predetermined thickness. Thus, excessive Ni in an amount equal to the thickness of the metal layer remains in the crystallized silicon film. Therefore, a TFT of polycrystalline silicon contaminated with the excessive Ni is unable to be used as a switching device due to degraded device characteristics.
Moreover, it takes more than 10 hours to crystallize silicon and the crystallization temperature is not that low. Thus, the time and temperature required for this process are unacceptable.
Metal induced lateral crystallization [hereinafter abbreviated MILC, S. W. Lee & S. K. Joo, IEEE Electron Device Lett., 17(4), P.160, (1996)] as an alternative method has been proposed lately.
MILC as shown in
FIG. 2
is performed such that silicon crystallization is induced laterally in a predetermined region which has been crystallized by MIC. In MILC, a portion of amorphous silicon
22
-
1
contacted with a specific metal
23
is crystallized by MIC, and a boundary of the crystallized silicon region
22
-
1
becomes a seed for crystallizing laterally the adjacent portion of the amorphous silicon
22
-
2
which is not directly contacted with the metal. Unfortunately, the crystallization speed of MILC is slow.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a method of crystallizing a silicon film and a method of manufacturing a liquid crystal display apparatus which achieve a silicon crystallization at a low temperature or a room temperature by increasing a temperature of an amorphous silicon film to be crystallized, by generating heat by applying voltage to a heat generating conductive layer.
In addition, preferred embodiments of the present invention provide a method of crystallizing a silicon film which greatly decreases the silicon crystallization time and power consumption by concentrating the Joule heat from the heat generating layer onto the amorphous silicon which is to be crystallized to define an active layer.
Additional features and advantages of the present invention will be set forth in the detailed description which follows and in part will be apparent from the detailed description, or may be learned by practice of the invention. The advantages, improvements, benefits and other aspects of the present invention are achieved by the various preferred embodiments particularly explained in the detailed description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purposes of the present invention, as embodied and broadly described, a method according to a preferred embodiment of the present invention includes the steps of forming an amorphous silicon film on an insulating substrate, forming a heat generating conductive layer over the amorphous silicon film, and applying a predetermined voltage to the heat generating conductive layer wherein electric current flows through the heat generating conductive layer to the amorphous silicon film so as to maximize crystallization of the amorphous silicon layer.
Another preferred embodiment of the present invention includes the steps of forming an amorphous silicon film and a heat generating conductive layer on a substrate in the same plane, and increasing a temperature of the amorphous silicon film by applying a predetermined voltage to the heat generating conductive layer wherein heat is generated from the heat generating conductive layer.
In another preferred embodiment of the present invention, a method includes the steps of forming a heat generating conductive layer on an insulating substrate, forming an insulating layer on the heat generating conductive layer, forming an amorphous silicon film on the insulating layer, and applying a predetermined voltage to the heat generating conductive layer wherein electric current is transmitted through the heat generating conductive layer to the amorphous silicon film.
In another preferred embodiment of the present invention, a method includes the steps of forming an active layer of amorphous silicon on a substrate, forming a first insulating layer on the substrate including the active layer, forming a gate pattern on the first insulating layer wherein the gate pattern includes a gate line having a gate electrode, a connecting bar connecting the gate line to other gate lines, a connecting bar pad, a test electrode, and a test electrode pad, doping the active layer with impurities while using the gate electrode as a mask, forming a second insulating layer over the substrate, exposing portions of the active layer doped
Choi Jae-Beom
Lee Kyung-Eon
Bowers Charles
LG. Philips LCD Co. Ltd.
Schillinger Laura M
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