Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-06-28
2001-12-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S455000, C438S458000
Reexamination Certificate
active
06326247
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the design of field effect transistors (FETS) and, more particularly, to a method of forming a metal oxide silicon (MOS) transistor structure including both fully depleted and partially depleted devices.
BACKGROUND OF THE INVENTION
As is known in the art, transistors such as metal oxide silicon (MOS) transistors, have been formed in isolated regions of a semiconductor body such as an epitaxial layer which was itself formed on a semiconductor, typically bulk silicon, substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N
+
type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P
+
type conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N
+
to P
+
spacing and hence higher packing density due to ease of isolation; and higher “soft error” upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources in drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g. metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
Conventional SOI FET's have floating bodies in which the body or channel region of the FET is located on an insulator and not electrically connected to a fixed potential. These devices are known as partially depleted SOI devices and have the aforementioned advantages and disadvantages. Fully depleted SOI devices are those in which the layer of semiconductor is sufficiently thin, such that the entire thickness of the body regions is depleted of majority carriers when in the off state and both diffusions are at ground. Fully depleted devices offer additional advantages, such as reduced short channel effect, increased transconductance and reduced threshold voltage sensitivity to changes in body doping. Furthermore, the kink effects and threshold voltage shifts caused by body charging in partially depleted devices are reduced. The fully depleted devices do not have a neutral region in the channel and thus do no allow for charging and discharging of the body corresponding to he change in threshold voltage. Additionally, the fully depleted devices do no show hysterisis effect. Therefore, it is advantageous to be able to form a semiconductor wafer with both partially depleted and fully depleted devices based on the desired characteristics of the device for a given implementation.
SUMMARY OF THE INVENTION
The present invention provides a method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. The present invention accomplishes this end by providing a silicon semiconductor having an oxide layer thereon. At least one trench is then etched into the oxide layer. A substrate material layer is then deposited onto the oxide layer filling the at least one trench and forming an insulating layer having regions of a first thickness at the at least one trench and regions of a second thickness everywhere except the at least one trench. The substrate layer is then ground and polished down to a desirable thickness. The device can then be flipped over and partially depleted transistor devices can then be formed over the regions of the first thickness and fully depleted transistor devices can be formed over regions of the second thickness.
One aspect of the invention relates to a method of forming an SOI MOSFET structure. The method comprises the steps of providing an insulating layer disposed over a semiconductive layer and etching at least one trench in the insulating layer. A substrate material is deposited over the insulating layer, which fills the at least one trench to form an insulating layer having a first thickness region and a second thickness region. The structure is then flipped over to expose the semiconductive layer. A partially depleted device in the semiconductive layer is formed over the first thickness region and a fully depleted device in the semiconductive layer is formed over the second thickness region.
Another aspect of the invention relates to an SOI MOSFET structure. The SOI MOSFET structure comprises an oxide layer disposed over a semiconductive layer and a substrate layer over the oxide layer. The substrate layer fills at least one trench disposed in the oxide layer. The at least one trench forms regions of the oxide layer having a first thickness and the remaining regions of the oxide layer are of a second thickness. The structure is flipped for forming partially depleted devices over the regions of first thickness and for forming fully depleted devices over the regions of a second thickness.
Yet another aspect of the invention relates to a method of forming fully depleted devices and partially depleted devices on the same semiconductor wafer. The method comprises the steps of providing an oxide layer disposed over a semiconductive layer and etching at least one trench in the oxide layer. A substrate material is deposited over the oxide layer and fills the at least one trench to form an insulating layer having a first thickness region and a second thickness region. A top surface of the substrate layer is reduced to a thickness suitable for forming a back gate. The semiconductor wafer is flipped and at least one partially depleted transistor device is formed over the first thickness region and at least one fully depleted transistor device is formed over the second thickness region.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
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Buynoski Matthew S.
Krishnan Srinath
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Anya Igwe U.
Smith Matthew
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