Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-01-31
2004-03-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06711725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to automatic layout of one or more elements of an integrated circuit, especially analog elements, and, more particularly, to the creation of conformal outlines used in the layout of these elements.
2. Brief Description of the Prior Art
In order to realize the high levels of integration that are occurring with system-on-chip designs, analog and digital functionality are being included on more semiconductor chips than ever. As more of these mixed signal chips are created, automation for the layout of the analog segments of these chips is required. Currently, this is an almost completely manual process.
An analog cell is typically a circuit, such as an operational amplifier or comparator, that includes between ten and one hundred elements, such as transistors, resistors and capacitors. In order to automatically lay out these elements to create a circuit, a large amount of detailed geometry needs to be optimized. For example, the placement of elements needs to take maximal advantage of design rules to create a compact and correct layout. One aspect of detailed geometric creation that can have a dramatic impact on the compactness and correctness of an analog cell layout is the well and latchup of protection geometry.
In a typical silicon semiconductor process, mask layers are created where each N-well is created and where each P-well is created. All N-type transistors must be surrounded by a P-type well and vice versa. These wells need to be electrically connected to the correct voltages or the transistors may not perform optimally, and in the worst case will not work at all. The geometry used to electrically connect the well to the rest of the circuitry is referred to as latchup protection geometry.
While the problems of creating wells and latchup protection geometry also occur in the layout of digital circuits, the solutions used to create well and latchup protection geometry for digital layouts are different than the solutions required for layout of analog cells. Specifically, for most digital cells, the transistors are very similarly sized and small. These transistors tend to share active regions in addition to sharing well geometry. The methodology most often used to create digital cells is to first define the areas of the cell where the P and N wells are positioned and then to place the transistors in those areas. In contrast, in an analog layout, the devices may be much larger and may also have differing sizes. Therefore, it is preferred to first place the devices, then form the wells around the devices.
Another difference between digital cell layout and analog cell layout is the voltage to which each well is connected. For digital layouts, the wells are almost always tied to power and ground. In contrast, analog circuits tend to have more wells that are tied to voltages other than power and ground.
In general, the rules on how a well geometry is created simply specify that the well geometry must enclose certain geometry of the devices by given amounts. The rules for where latchup protection must be formed in a well geometry, however, are more complicated. Specifically, latchup protection must be formed in the well area with the devices and must be placed so that it can effectively keep the entire well at a desired voltage. In general, this latter condition is expressed as a radius from which all the devices in the well must be located from the latchup protection geometry.
In addition to these physical rules, there are constraints on the performance of an automated solution for the creation of well and latchup protection geometry. Namely, it must be fast enough to be used in automatic layout where a large number of candidate solutions, each having well and latchup protection geometry, may need to be evaluated. The solution must also be fast enough to be used in an interactive mode to assist the designer with manual placement.
The wells that are created must also satisfy aesthetic constraints in order to be acceptable to designers. These constraints can be roughly expressed to be that the well shapes should have low complexity. Shapes with rough, jagged edges are generally not acceptable to designers. Moreover, designers prefer each well group to be as large as possible. However, this latter preference is in tension with the goal of any automated well layout system to minimize the well area utilized to receive the desired circuits.
It is, therefore, an object of the present invention to overcome the above problems and others by providing an automated method for creating well geometries for circuits, especially analog circuits. It is also an object of the present invention to minimize the area of the generated well geometry while, at the same time, avoiding overlap between the generated well geometry and one or more areas of an integrated circuit design where it is desired to avoid placing circuits or elements of a circuit. Still other objects will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.
SUMMARY OF THE INVENTION
Accordingly, we have invented a method of creating a conformal outline for layout of one or more devices on an integrated circuit. The method includes defining a plurality of input rectangles in a Cartesian coordinate system having a first axis and second axis, with each input rectangle having two edges parallel to the first axis and two sides parallel to the second axis. Coordinates on the first axis where the sides of each input rectangle sides reside are acquired and a sorted list is formed from the acquired coordinates. A variable I is initialized with the value of two (2) and first and second candidate rectangles having one of their respective sides positioned at the smallest and largest coordinates in the sorted list, respectively, are identified from the input rectangles. The other of the sides of the respective first and second candidate rectangles are set equal to the coordinate on the first axis stored in the I
th
position in the sorted list, thereby forming a shared side. For each candidate rectangle having coordinates on the first axis which overlap coordinates of one or more input rectangles on the first axis, the lengths of the sides of the candidate rectangles are modified as necessary so that they extend from the maximum to the minimum second axis coordinates of the one or more input rectangles. If the shared side with respect to one candidate rectangle does not coincide with or overlap the shared side with respect to the other candidate rectangle, the length of the shared side with respect to the one candidate rectangle is modified as necessary so that it coincides with or overlaps the shared side with respect to the other candidate rectangle.
The method can also include the step of initializing a Best Solution variable that includes a cost.
The method can further include the steps of determining a cost of the candidate rectangles and, when the cost of the candidate rectangles is more advantageous then the cost of the Best Solution, updating the Best Solution with the position of the candidate rectangles in the Cartesian coordinate system and the cost determined therefor.
Next, the variable I is incremented by one (1) and a determination is made if I equals the number of coordinates in the sorted list. If not, the shared side is stepped or moved to the coordinate on the first axis stored in the I
th
position in the sorted list. For each candidate rectangle having coordinates on the first axis which overlap coordinates of one or more input rectangles on the first axis, the lengths of the sides of the candidate rectangle are modified as necessary so they extend from the maximum to the minimum second axis coordinates of the one or more input rectangles. If the shared side with respect to one candidate rectangle does not coincide with or overlap the shared side with respect to the other candidate rectangle, the length of the shared side with respect to one rectangle is modified as necessary
Fallon Elias L.
Reaves Donald B.
Rutenbar Rob A.
Neolinear, Inc.
Siek Vuthe
Tat Binh
Webb Ziesenheim & Logsdon Orkin & Hanson, P.C.
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