Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
1999-10-27
2001-04-24
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C257S626000
Reexamination Certificate
active
06222255
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to wafer fabrication and, more specifically, to a method of creating an interconnect in a substrate and a semiconductor device employing the interconnect.
BACKGROUND OF THE INVENTION
As the complexity of integrated circuits increases, numerous approaches have been taken to solve the problem of expediently making electrical connection to and between individual devices. This is an important problem in integrated circuit fabrication because not only do electrical contacts and interconnections require space on the integrated circuit chip, but the complexity of the interconnections frequently requires the metallizations to be on more than one level. The former considerations require minimization of the size of the metallization, and the latter consideration introduces processing complexity.
In a typical multilevel fabrication sequence, windows or vias are first opened in a dielectric layer to expose selected portions of the underlying substrate and then filled with a metal. The substrate of the semiconductor may be used as an underlying material, and thus may include the silicon wafer, source and drain regions, prior interconnections, etc. Metal runners that form electrical connection to other portions of the semiconductor fill the windows that are formed on the dielectric. This is typically done by blanket depositing a metal and then patterning it. Of course, care must be taken to insure that the runners are properly aligned so that they contact the windows.
In such conventional processes, the metal is defined after the dielectric is deposited. Thus, there is a dielectric etch followed by the deposition and patterning of the metal. As the industry requirements for semiconductor sizes continue to decrease, a difficulty arises in that the metal patterning becomes very difficult to control. More specifically, the anisotropic etching of the metal may not be controlled very well. Moreover, this may become of particular concern as copper increasingly becomes the metal of choice over aluminum as the conductive metal. However, the use of copper presents a further problem in that it is harder to etch in a controlled manner.
Due to these problems, and as semiconductor sizes continue to decrease, forming a reliable interconnect structure with metal etching, whether copper or aluminum, has become difficult. In current processes, a photoresist is deposited over the metal in which the interconnect is to be formed, for example, see S. Wolf,
Silicon Processing for the VLSI Era,
Vols. I, II, and III, Latice Press, which are incorporated herein by reference. After patterning and exposure, the unexposed photoresist is removed and the etch continues to proceed into the underlying metal.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides methods of creating a cavity to contain an interconnect leading to a location within a substrate that has a first dielectric layer of a first etch rate formed over the location, and a semiconductor device containing such an interconnect. One embodiment of the method includes the steps of: forming a second dielectric layer on the first dielectric layer wherein the second dielectric layer has a second etch rate slower than the first etch rate, forming a photoresist layer on the second dielectric layer and etching into the first and second dielectric layers to form the cavity leading to the location.
The present invention therefore introduces the broad concept of varying the etch rate of adjacent dielectric layers to control the dimensions of a cavity to be formed beneath the layers.
In another embodiment, the method comprises the steps of forming a nitride layer on the oxide layer wherein the nitride layer has a second etch rate slower than the first etch rate, forming a photoresist layer on the nitride layer and etching into the oxide and nitride layers to form the cavity leading to the location.
In yet another embodiment, the present invention provides a semiconductor device comprising: a substrate having a conductive layer located therein, a first dielectric layer of a first etch rate located over a particular location on the conductive layer, a second dielectric layer located on the first dielectric layer, wherein the second dielectric layer has a second etch rate slower than the first etch rate, a photoresist layer located on the second dielectric layer, and a conductive substance deposited into a cavity in the first and second dielectric layers to form an interconnect leading to the particular location.
REFERENCES:
patent: 3945030 (1976-03-01), Seales
patent: 6019906 (2000-02-01), Jang et al.
patent: 6046100 (2000-04-01), Ramaswami et al.
patent: 6080529 (2000-06-01), Ye et al.
Clark Sheila V.
Lucent Technologies - Inc.
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