Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2009-04-30
2011-12-27
Lin, Sun (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S106000, C716S118000, C716S139000
Reexamination Certificate
active
08086990
ABSTRACT:
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.
REFERENCES:
patent: 6831292 (2004-12-01), Currie et al.
patent: 6881632 (2005-04-01), Fitzgerald et al.
patent: 7337420 (2008-02-01), Chidambarrao et al.
patent: 7437260 (2008-10-01), Ausserlechner et al.
patent: 7440861 (2008-10-01), Ausserlechner et al.
patent: 7542891 (2009-06-01), Lin et al.
patent: 2003/0173588 (2003-09-01), Bianchi
patent: 2007/0202652 (2007-08-01), Moroz et al.
patent: 2007/0202663 (2007-08-01), Moroz et al.
patent: 2007/0204250 (2007-08-01), Moroz et al.
Bianchi, R.A. et al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on MOSFET Electrical Performance,” IEEE IEDM Tech. Digest, Dec. 2002, pp. 117-120.
Eneman, G., et al., “Layout Impact on the Performance of a locally Strained PMOSFET,” 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005, pp. 22-23.
Kanda, Y., A Graphical Representation of the Piezoresistance Coefficients in Silicon, IEEE Transactions on Electron Devices, ED-29(1), Jan. 1982.
Moroz, et al., “Options at the 45 nm node include engineerred substraces,” Solid State Technology, Jul. 2005.
Moroz, V. et al., “Analyzing strained-silicon options forstress-engineering transistors,” Solid State Technology, Jul. 2004.
Nouri, F. et al., “A Systematic Study of Trade-offs in Engineering a Locally Strained pMOSFET,” Proc. IEDM, 2004, pp. 1055-1058.
Smith, et al., “Exploring the Limits of Stress-Enhanced Hole Mobility,” IEEE Electron Device Letters, 26(9), Sep. 2005.
Smith, C.S. et al., “Piezoresistance Effect in Germanium and Silicon,” Physical Review, 94(1), Apr. 1954.
Thompson, S.E. et al., “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions on Electron Devices, 2004.
Xuemei, Xi (Jane) et al., “BSIM4.3.0 Model, Enhancements and Imrpovements Relative to BSIM4.2.1,” University of California at Berkeley (2003), available at http://www-devices.eecs.berkeley.edu/˜bsim3/BSIM4/BSIM430/doc/BSIM430—Enhancement.pdf.
Smit G.D.J. et al., “PSP 102.0,” The Pennsylvania State University and Philips Research, Jun. 2006, 112 pp.
Gildenblat G. et al., “PSP Model,” Dept. of Electrical Engineering, The Pennsylvania State University and Philips Research, Aug. 2005, 82 pp.
Lin Xi-Wei
Moroz Victor
Pramanik Dipankar
Haynes Beffel & Wolfeld LLP
Lin Sun
Synopsys Inc.
Wolfeld Warren S.
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