Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-18
2002-08-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S679000, C438S687000
Reexamination Certificate
active
06432821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of electroplating, and more specifically, to electroplating of copper onto wafers to fill damascene structures.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as, for example, silicon dioxide. These conductive materials are typically a metal or metal alloy. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These electrically conductive structures are often referred to as contacts or vias.
Other advances in semiconductor manufacturing technology, such as the ability to repeatably pattern very small features, have led to the integration of millions of transistors, each capable of switching at high speed. A consequence of incorporating so many fast switching transistors into an integrated circuit is an increase in power consumption during operation. One technique for increasing speed while reducing power consumption is to replace the traditional aluminum and aluminum alloy interconnects found on integrated circuits with a metal such as copper, which offers lower electrical resistance. Those skilled in the electrical arts will appreciate that by reducing resistance, electrical signals may propagate more quickly through the interconnect pathways on an integrated circuit. Furthermore, because the resistance of copper is significantly less than that of aluminum, the cross-sectional area of a copper interconnect line, as compared to an aluminum interconnect line, may be made smaller without incurring increased signal propagation delays based on the resistance of the interconnect. Additionally, because the capacitance between two electrical nodes is a function of the overlap area between those nodes, using a smaller copper interconnect line results in a decrease in parasitic capacitance. In this way, replacing aluminum-based interconnects with copper-based interconnects provides, depending on the dimensions chosen, reduced resistance, reduced capacitance, or both.
As noted above, copper has electrical advantages, such as lower resistance per cross-sectional area, the ability to provide for reduced parasitic capacitance, and greater immunity to electromigration. For all these reasons manufacturers of integrated circuits find it desirable to include copper in their products.
While advantageous electrically, copper is difficult to integrate into the process of making integrated circuits. As is known in this field, copper can adversely affect the performance of metal oxide semiconductor (MOS) field effect transistors (FETs) if the copper is allowed to migrate, or diffuse, into the transistor areas of an integrated circuit. Therefore copper diffusion barriers are used to isolate copper metal from those transistor areas. Additionally, unlike aluminum based metal interconnect systems which are formed by subtractive etch processes, copper interconnects are typically formed by damascene metal processes. Such processes are also sometimes referred to as inlaid metal processes.
In a damascene process, trenches are formed in a first layer, and a metal layer is formed over the first layer including the trenches. Excess metal is then polished off leaving individual interconnect lines in the trenches.
FIG. 1
shows a schematic cross-section of a partially processed wafer with a postplating, pre-polish damascene structure
100
. In this case, a dual damascene structure has been formed with a trench portion
108
and a via portion
110
. Trench
108
and via
110
are formed by first patterning, i.e., making openings in, interlayer dielectric
102
. A layer
104
that acts as a barrier to copper diffusion is then formed over the surfaces of patterned interlayer dielectric
102
, a seed layer is formed over barrier layer
104
, and copper or copper alloy is plated over these.
Accordingly, there is a need for electroplating methods, materials, and apparatus to that can form, on wafers, very narrow conductive interconnects made from materials such as copper and copper alloys.
REFERENCES:
patent: 6245676 (2001-06-01), Ueno
patent: 6297157 (2001-10-01), Lopatin et al.
patent: 6340633 (2002-01-01), Lopatin et al.
patent: 2002/0004301 (2002-01-01), Chen et al.
patent: 2002/0022363 (2002-02-01), Ritzdorf et al.
Collazo-Davila Christopher
Dubin Valery M.
Jentz Dave W.
No associations
LandOfFree
Method of copper electroplating does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of copper electroplating, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of copper electroplating will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2967595