Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-23
2002-03-19
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S723000, C438S786000
Reexamination Certificate
active
06358841
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of a planarized structure of copper or other conductor materials embedded in a low dielectric constant insulator, such as HSQ (hydrogen silsesquioxane). HSQ, an inorganic source of silicon oxide, has the chemical formula (HSiO
3/2
)n and has a dielectric constant of about 2.9.
(2) Description of the Related Art
In the fabrication of semiconductor integrated circuits device element geometries have shrunk to and below 0.5 microns. At the same time the demands upon the interlevel dielectric layers and the conductive materials used for device interconnections have become more stringent. The interlevel dielectric layers must fill gaps with higher aspect ratios and must provide lower dielectric constants in order to reduce both interlevel and intra-level capacitance. Capacitance markedly increases when the spacing between conductive elements decreases below 0.5 microns and it becomes imperative that low dielectric constant material be used as both the interlevel and intra-level insulating material. Circuit speed is a function of the RC constant of the integrated circuit devices, where R is the resistance of the conducting portions of the integrated circuit and C is the capacitance, both interlevel and intra-level, of the integrated circuit structure. It is desirable that the RC constant be low, so a high conductivity material, such as copper is preferred for the interconnection elements of the integrated circuit and a low dielectric constant material, such as HSQ (hydrogen silsesquioxane) is preferred as the interlevel and intra-level insulating layers.
Furthermore, in order to meet the levels of integration required in circuits having geometries of less than 0.5 microns it is necessary to have multiple levels of inter-connection wiring and processing methods must be employed which maintain layer planarity as additional layers of interconnection patterns are added to the device structure, since it is difficult to lithographically image and pattern layers applied to rough surfaces. To this end, CMP (Chemical Mechanical Polishing) has been used to provide smooth topography on insulating layers deposited on semiconductor substrates. Also, CMP can be used to remove different layers of material from the surface of a semiconductor substrate. For example, following contact hole formation in an insulating layer, a metallization layer is deposited and then CMP is used to produce planar metal plugs embedded in the insulating layer. Similarly, interconnection wiring can be formed by first etching wiring channels into an insulating layer and then depositing a metallization layer onto the insulating layer and into the etched channels. CMP is then used to remove the metallization layer from the surface of the insulating layer, leaving the metallization material embedded in the etched channels.
An important challenge in CMP, when selectively removing a second material layer from a first material layer, is to remove the second material without removing an excessive amount of the underlying first material layer. In the state-of-the-art application of CMP to formation of co-planar structures of copper conductive material embedded in HSQ insulating material a major deficiency exists because the CMP polishing slurries used to remove copper, also, remove HSQ at a high rate and therefore the HSQ must be protected with a polish stop layer, such as PECVD (Plasma Enhanced Chemical Vapor Deposited) oxide. The incorporation of PECVD oxide (which has a dielectric constant of about 4.0) into the structure negatively impacts the RC constant of the integrated circuit and limits the lowering of the RC constant which could be obtained when solely using HSQ (which has a dielectric constant of about 2.9) as the insulating material.
Numerous inventions address the formation of dielectric layers using HSQ, but none provide a suitable solution for combining CMP of copper or other conductive materials to form coplanar structures of copper or otter conductive materials embedded in HSQ insulating material. For example, U.S. Pat. No. 5,607,773 entitled “Method Of Forming A Multilevel Dielectric” granted Mar. 4, 1997 to Byron T. Ahlburn et al. describes a method of forming a silicon oxide dielectric layer from a hydrogen silsesquioxane (HSQ) source.
U.S. Pat. No. 5,334,554 entitled “Nitrogen Plasma Treatment To Prevent Field Device Leakage In VLSI Processing” granted Aug. 2, 1994 to Kwang-Ming Lin et al. shows a method of forming multiple layer metallurgy, spin-on-glass multilayer metallurgy structures in which a silicon oxide dielectric layer is exposed to a nitrogen containing plasma at a temperature of less than about 450° C. The nitrogen plasma treatment is responsible for the removal of the charge buildup problem in final product.
U.S. Pat. No. 5,506,177 entitled “Fabrication Process For Multilevel Interconnections In A Semiconductor Device” granted Apr. 9, 1996 to Koji Kishimoto et al. describes a method of forming an inter layer insulation layer of SOG (Spin-On-Glass) made from hydrogen silsesquioxane source. The method includes a pre-bake of the SOG by a first heat treatment at 200° C. for 2 min., followed by reflow of the SOG by a second heat treatment at a temperature higher than that of said first heat treatment.
U.S. Pat. No. 5,059,448 entitled “Rapid Thermal Process For Obtaining Silica Coatings” granted Oct. 22, 1991 to Grish Chandra et al. describes a method for forming an insulation layer from a hydrogen silsesquioxane source resin. The method includes a RTP (Rapid Thermal Process) step in order to heat the substrate sufficiently to convert the hydrogen silsesquioxane resin to a silica coating.
U.S. Pat. No. 4,847,162 “Multilevel Ceramics Coatings From The Ceramification Of Hydrogen Silsesquioxane Resin In The Presence Of Ammonia” granted Jul. 11, 1989 to Loren A. Haluska et al. describes a method for forming an insulation layer from a hydrogen silsesquioxane source resin in which a coating layer of the hydrogen silsesquioxane source resin is heated in the presence of NH
3
at a temperature between 200and 400° C.
The present invention is directed to a novel method of fabricating a planarized structure on a semiconductor substrate, wherein a conductive material is embedded in a low dielectric constant insulator, such as HSQ (hydrogen silsesquioxane). In the method of the present invention the HSQ layer is treated in NH
3
or N
2
plasmas to cause reduced CMP removal rates of the HSQ allowing CMP to be used to selectively remove the conductive material over the treated HSQ without significant attack of the treated HSQ. The method of the present invention does not require a CMP protection layer, such as deposited oxide, on top of the HSQ layer.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of forming a planarized integrated circuit in which the interconnection metallization comprises copper or other conductor materials embedded in a low dielectric constant insulator, such as HSQ (hydrogen silsesquioxane).
A more specific object of the present invention is to provide an improved method of forming a planarized integrated circuit, wherein the planarized structure is formed by CMP of copper or other conductor materials after deposition of copper or other conductor materials onto an HSQ layer having etched channels therein.
Another object of the present invention is to provide an improved method of forming on a semiconductor substrate a planarized structure of copper or other conductive materials embedded in low dielectric constant HSQ material, in which CMP of the copper or other conductive materials is performed without excessive removal of low dielectric constant HSQ material.
In accordance with the present invention, the above and other objectives are realized by using a method of fabricating a planarized structure on a semiconductor substrate, wherein a conductive
Bao Tien I.
Jang Syun-Ming
Ackerman Stephen B.
Chaudhuri Olik
Peralta Ginette
Saile George O.
Taiwan Semiconductor Manufacturing Company
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