Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-03-05
2004-10-05
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S717000, C438S014000
Reexamination Certificate
active
06800562
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to the field of semiconductor manufacturing and, more particularly, to a method of controlling wafer charging effects due to manufacturing processes, and a system for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
As device dimensions have continued to decrease, the ability to precisely form very small features to their desired dimension has become more important. Variations in the physical dimensions of such features can adversely impact device performance and reduce product yields. For example, the critical dimension and profile of gate electrode structures of transistors is one area where a very high degree of precision is desired. Absent precise control of such dimensions, adverse consequences may follow. For example, if the critical dimension of the gate electrode is greater than the target or design critical dimension, the transistor may not operate as fast as desired by the product design requirements. Conversely, if the critical dimension of the gate electrode structure is less than the target value, standby leakage currents may be higher than desired. This situation is particularly problematic for integrated circuit devices intended for mobile telecommunication applications and those intended for mobile computing devices.
Various manufacturing processes, such as etching, photolithography, deposition, heating and ion implantation processes, may be performed many times during the course of manufacturing integrated circuit products. Some of these processes may involve a charging mechanism that may introduce charged ions into the substrate or adjacent areas or structures. For example, some of these processes may involve the generation of a plasma, e.g., reactive ion etching, plasma enhanced chemical vapor deposition (PECVD), etc. As a more specific example, a plasma etching process, typically anisotropic in nature, may be performed to define a polysilicon gate electrode on a transistor and a floating gate or control gate on a flash memory device.
During the performance of such processes, an undesirable charge may be stored on part of the device or material, e.g., on a layer of insulating material, such as silicon dioxide, on a polysilicon gate electrode, on a deposited layer of polysilicon, or a combination thereof, etc. This is sometimes referred to as wafer charging. The wafer may also be subjected to charging via static charging and surface charging mechanisms.
Wafer charging is undesirable from many points of view. For example, such wafer charging may alter the electrical characteristics of the particular device manufactured. By way of example, due to wafer charging, the threshold voltage (V
T
) of a transistor may be different than the value expected by the design process, i.e., the actual threshold voltage of the manufactured device may be less than or greater than anticipated. Variations in such electrical parameters may ultimately adversely impact or degrade device performance.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
The present invention is generally directed to various methods of controlling wafer charging effects due to manufacturing processes, and a system for performing same. In one illustrative embodiment, the method comprises identifying a process metric associated with a process operation that is capable of generating a charge that is stored in at least one of a process layer and a feature formed above a substrate, establishing an allowable range for the process metric based upon data obtained from at least one electrical test performed on at least one semiconductor device subjected to the process operation, performing the process operation and indicating an alarm condition if the process metric associated with the process operation is not within the allowable range.
In a further illustrative embodiment, the method comprises identifying a process metric associated with a process operation that involves generation of a plasma, establishing an allowable range for the process metric based upon data obtained from at least one electrical test performed on at least one semiconductor device subjected to the process, performing the process operation on a semiconducting substrate, and indicating an alarm condition if the process metric associated with the process operation is not within the allowable range.
In another illustrative embodiment, the method comprises identifying a process metric associated with a process operation that involves generation of a plasma, establishing an allowable range for the process metric based upon data obtained from at least one electrical test performed on at least one semiconductor device subjected to the process, performing the process operation on a semiconducting substrate, and adjusting at least one parameter of the process operation if the process metric is not within an allowable range.
In yet another illustrative embodiment, the method comprises identifying a process metric associated with a process operation that involves generation of a plasma, establishing an allowable range for the process metric based upon data obtained from at least one electrical test performed on at least one semiconductor device subjected to the process, performing the process operation on a semiconducting substrate, determining a value for the process metric during the process operation performed on the semiconducting substrate, and performing a subsequent process operation on the processed semiconducting substrate to reduce electrical charge stored in at least one of a process layer and a feature formed during the process operation if the process metric is not within an allowable range.
In still a further illustrative embodiment, the method comprises identifying a process metric associated with a plasma etching process operation, establishing an allowable range for the process metric based upon data obtained from at least one electrical test performed on at least one semiconductor device subjected to the plasma etching process operation, performing the plasma etching process operation on a semiconducting substrate, and indicating an alarm condition if the process metric associated with the plasma etching process operation is not within an allowable range.
REFERENCES:
patent: 2003/0228532 (2003-12-01), Mui et al.
Cusson Brian K.
Sonderman Thomas J.
Advanced Micro Devices , Inc.
Le Dung A.
Williams Morgan & Amerson P.C.
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