Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-04-05
2005-04-05
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S243000, C438S246000, C438S386000, C438S389000, C438S430000, C438S431000
Reexamination Certificate
active
06875669
ABSTRACT:
A method of controlling the top width of a deep trench. A conductive layer is formed on the trench over a substrate of polysilicon with a recessed structure. An additional layer of amorphous silicon (α-Si) is deposited onto the polysilicon. After subsequent oxidation, the amorphous silicon is converted to SiO2. According to the invention, the top width of a deep trench is controlled, protecting bit lines from sub-threshold leakage.
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patent: 6437381 (2002-08-01), Gruening et al.
patent: 6777303 (2004-08-01), Schrems et al.
patent: 20020024082 (2002-02-01), Tsunashima et al.
patent: 20040241953 (2004-12-01), Wang et al.
Hsu Ping
Wang Jiann-Jong
Nanya Technology Corporation
Quintero Law Office
Trinh Michael
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