Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2000-07-25
2003-09-16
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S103000
Reexamination Certificate
active
06622196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of controlling a semiconductor memory device, and more particularly to a method of controlling a semiconductor memory device on which an AND-type flash memory is mounted.
2. Description of the Background Art
In recent years, a card-type memory device, such as a flash ATA (AT attachment) card and a compact flash card, has been proposed as an external memory device for a computer. This is composed of a large-capacity flash memory for data storage, a controller for controlling and managing the flash memory and a peripheral circuit. The controller performs both management of the interface between the memory device and a host system, such as a personal computer, and control and management of the flash memory according to instructions of the host system.
In recent, capacity of the flash memory has increased and a memory having a capacity of 32 megabits has begun to be used for one chip. Accordingly, it has become standard that a card capacity is determined in a multiple manner, as 32 megabits, 64 megabits and 128 megabits.
Therefore, to obtain a card having intermediate capacity, it is necessary to mount a plurality of flash memories smaller in capacity than 32 megabits, to mount a flash memory larger in capacity than 32 megabits and format the memory in smaller capacity, or to combine a plurality of types of flash memories having different capacities.
The case of combining a plurality of types of flash memories having different capacities is problematic. The size per flash sector (hereinafter, referred to as flash sector size) of an AND-type flash memory having 64 megabits (hereinafter, referred to as 64-Mbit memory) is 512 bytes and the flash sector size of an AND-type flash memory having 256 megabits (hereinafter, referred to as 256-Mbit memory) is 2048 bytes.
Accordingly, the capacities of the 64-Mbit memory and the 256-Mbit memory are calculated as follows:
“64-Mbit memory”
The flash sector size is; 512 bytes (data area)+16 bytes (control area)=528 bytes,
The capacity is; 528 bytes×16384 sectors×8=69206016 bits.
“256-Mbit memory”
The flash sector size is; 2048 bytes (data area)+64 bytes (control area)=2112 bytes,
The capacity is; 2112 bytes×16384 sectors×8=27682406 bits.
In the card-type memory device, operations of read, program (write) and erase are performed in units of 512 bytes. For this reason, in order to control the flash memories having different flash sector sizes, controllers in conformity with the respective specifications of the flash memories and firmwares for managing the sectors are needed, and merely combining a plurality of types of flash memories having different capacities makes the constitution of the card-type memory device more complicate.
SUMMARY OF THE INVENTION
The present invention is directed to a method of controlling a semiconductor memory device. According to a first aspect of the present invention, the method of controlling a semiconductor memory device controls operations of at least one first memory element and at least one second memory element which are different from each other, and in the method of the first aspect, a first access operation is performed on the at least one first memory element when a memory area to be externally accessed belongs to the at least one first memory element, and a second access operation is performed on the least one second memory element when the memory area to be externally accessed belongs to the at least one second memory element.
According to a second aspect of the present invention, in the method according to the first aspect, the at least one first memory element and the at least one second memory element each has a memory area consisting of a plurality of sectors, and the method comprises the steps of: (a) assigning logical sector numbers each not larger than a predetermined value to the plurality of sectors in the at least one first memory element and assigning logical sector numbers each larger than the predetermined value to the plurality of sectors in the at least one second memory element; and (b) designating the memory area to be externally accessed by the logical sector number and comparing a designated-sector number which is thus designated with the predetermined value.
According to a third aspect of the present invention, in the method according to the second aspect, the logical sector numbers assigned to the sectors in the at least one first memory element are arrayed in units of first predetermined number and the logical sector numbers assigned to the sectors of the at least one second element are arrayed in units of second predetermined number in the step (a), and the method further comprises the step of: (c) performing the first access operation and the second access operation in units of the first predetermined number and in units of the second predetermined number, respectively.
According to a fourth aspect of the present invention, in the method according to the third aspect, the at least one first memory element provides a plurality of first memory elements and the at least one second memory element provides a plurality of second memory elements, and a logical cluster number is assigned in common to the plurality of first memory elements in units of the first predetermined number and another logical cluster number is assigned in common to the plurality of second memory elements in units of the second predetermined number in the step (a).
According to a fifth aspect of the present invention, the method of controlling a semiconductor memory device controls operations of at least one first memory element having a first storage capacity and at least one second memory element having a second storage capacity twice as large as the first storage capacity, and in the method of the fifth aspect, the at least one second memory element is separately recognized as a first virtual memory element and a second virtual memory element each having the first memory capacity, and the same access operation as performed on the at least one first memory element is performed on each of the first and second virtual memory elements.
According to a sixth aspect of the present invention, in the method according to the fifth aspect, an extension signal indicating whether the first virtual memory element or the second virtual memory element a memory area to be externally accessed belongs to is generated together with a designated-address signal specifying the memory area to be externally accessed.
According to a seventh aspect of the present invention, in the method according to the sixth aspect, the at least one first memory element and the at least one second memory element each has a memory area consisting of a plurality of sectors, logical sector numbers are assigned to all the plurality of sectors, the logical sector numbers being different from one another, the logical sector numbers are arrayed in units of predetermined number in each of the at least one first memory element and the at least one second memory element, and the memory area to be externally accessed is accessed in units of the predetermined number.
According to an eighth aspect of the present invention, in the method according to the seventh aspect, the at least one first memory element and the at least one second memory element each has a predetermined number of input terminals for inputting the designated-address signal, and the extension signal is inputted to the at least one second memory element through a terminal among the input terminals of the at least one second memory element, the terminal corresponding to a redundant terminal among the input terminals of the at least one first memory element.
In the method of controlling a semiconductor memory device of the first aspect of the present invention, even when the first and second memory elements are mounted on one memory device, it is possible to control its operation with a single controller.
In the method of the second aspect of th
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Thai Tuan V.
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