Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-04-24
2004-11-23
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06822909
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a method of controlling program threshold voltage distributions of a dual cell electrically erasable and programmable charge trapping dielectric flash memory device.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, can store data in a “double-bit” arrangement. That is, one bit (i.e., a binary data value have two states, such as a logical one and a logical zero) can be stored using a charge storing cell on a first “side” of the memory device and a second bit can be stored using a complimentary charge storing cell on a second “side” of the memory device.
Programming of such a memory device can be accomplished, for example, by hot electron injection. Hot electron injection involves “pulsing” the device by applying appropriate voltage potentials to each of a gate and a drain of the memory device for a specified duration. During the programming pulse, the source is conventionally grounded. Following the programming pulse, a verify operation is carried out to ensure that the memory device stores a desired amount of charge corresponding the intended data value (or data state).
If the verify operation indicates that the memory device failed to become sufficiently programmed, the memory device is pulsed again with the same programming voltages as used during the earlier pulse. For example, the program voltages at 25 degrees C. can be about 9.8 volts (V) for the gate voltage (V
g
) and about 5.5 V for the drain voltage (V
d
). At 90 degrees C., V
g
can be about 10.5 V and V
d
can be about 5.5 V. The foregoing programming procedure is followed both for core memory cells (e.g., those cells used to store data by a customer of the memory unit) and for dynamic reference cells (e.g., those cells used to hold a reference amount of charge to establish a reference threshold voltage used during a read operation of the core memory cells).
The conventional program/verify operation can result in large program threshold voltage distributions. That is, a first program pulse may cause the memory cell to store a certain amount of charge, but that charge amount may not be sufficient enough to raise the threshold voltage (Vt) of the memory device over a verify threshold voltage. The next program pulse may place additional charge in the memory cell, for a total amount of stored charge that is needlessly greater than the amount of charge sufficient to raise the Vt of the memory device to pass the verify operation.
Large program distributions can be problematic when attempting to program and/or read memory devices that are configured to store discernable levels of charge. Accordingly, there exists a need in the art for improved control over program threshold voltage distributions of a dual cell memory device.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a method of programming a charge trapping dielectric memory device having a first charge storing cell and a second charge storing cell. The method can include a) applying an initial program pulse including initial gate, drain and source program voltages to the memory device to inject an amount of charge into a selected one of the first or second charge storing cells, the amount of charge corresponding to a charged program level; b) comparing a threshold voltage of the memory device with a verify threshold voltage; and c) if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one of the initial gate, drain and source program voltages is modified from the corresponding initial program voltage.
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Hamilton Darlene G.
Hsia Edward
Randolph Mark W.
Runnion Edward F.
Tanpairoj Kulachet
Advanced Micro Devices , Inc.
Renner , Otto, Boisselle & Sklar, LLP
Tran M.
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