Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-09-29
2011-10-04
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S042000, C714S004200, C710S301000
Reexamination Certificate
active
08032793
ABSTRACT:
In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.
REFERENCES:
patent: 5173689 (1992-12-01), Kusano
patent: 5317569 (1994-05-01), Ralph et al.
patent: 5499381 (1996-03-01), Shibamiya
patent: 5535192 (1996-07-01), Trubey et al.
patent: 6012150 (2000-01-01), Bartfai et al.
patent: 6032266 (2000-02-01), Ichinohe et al.
patent: 6138199 (2000-10-01), Fleischer
patent: 6336151 (2002-01-01), Seki
patent: 6389555 (2002-05-01), Purcell et al.
patent: 6496880 (2002-12-01), Ma et al.
patent: 6542961 (2003-04-01), Matsunami et al.
patent: 6662219 (2003-12-01), Nishanov et al.
patent: 6691245 (2004-02-01), DeKoning
patent: 6732218 (2004-05-01), Overtoom et al.
patent: 6732289 (2004-05-01), Talagala et al.
patent: 6938084 (2005-08-01), Gamache et al.
patent: 6986076 (2006-01-01), Smith et al.
patent: 7039827 (2006-05-01), Meyer et al.
patent: 7293195 (2007-11-01), Watanabe et al.
patent: 7350014 (2008-03-01), Kapoor et al.
patent: 7415551 (2008-08-01), Pescatore
patent: 2002/0188711 (2002-12-01), Meyer et al.
patent: 2002/0194371 (2002-12-01), Kadoi
patent: 2003/0120819 (2003-06-01), Abramson et al.
patent: 2003/0133712 (2003-07-01), Arikawa et al.
patent: 2003/0141093 (2003-07-01), Tirosh et al.
patent: 2004/0019726 (2004-01-01), Kelley et al.
patent: 2004/0019729 (2004-01-01), Kelley et al.
patent: 2004/0264472 (2004-12-01), Oliver et al.
patent: 2005/0015531 (2005-01-01), Yabuta et al.
patent: 2005/0089015 (2005-04-01), Tsuge et al.
patent: 2005/0102437 (2005-05-01), Pettey et al.
patent: 2005/0229034 (2005-10-01), Fujibayashi
patent: 2005/0240703 (2005-10-01), Nguyen et al.
patent: 2005/0246450 (2005-11-01), Enko et al.
patent: 2005/0270974 (2005-12-01), Mayhew
patent: 2005/0270988 (2005-12-01), DeHaemer
patent: 2006/0050722 (2006-03-01), Bury et al.
patent: 2006/0056400 (2006-03-01), Griggs
patent: 2006/0072615 (2006-04-01), Narad et al.
patent: 2006/0112199 (2006-05-01), Sonksen et al.
patent: 2006/0143311 (2006-06-01), Madukkarumukumana et al.
patent: 2006/0206655 (2006-09-01), Chappell et al.
patent: 63-308658 (1988-12-01), None
patent: 3-139751 (1991-06-01), None
patent: 5-307516 (1993-11-01), None
patent: 9-321804 (1997-12-01), None
patent: 11-203231 (1999-07-01), None
patent: 2001-101125 (2001-04-01), None
patent: 2002-64511 (2002-02-01), None
patent: 2002-342255 (2002-11-01), None
patent: 3091475 (2002-11-01), None
patent: 2003-174451 (2003-06-01), None
patent: 2004-15576 (2004-01-01), None
patent: 2004-104186 (2004-04-01), None
patent: 2004-145901 (2004-05-01), None
patent: 2004-186745 (2004-07-01), None
patent: 2004-532442 (2004-10-01), None
patent: 2004-355351 (2004-12-01), None
patent: WO-03/101144 (2003-12-01), None
David Mayhew and Venkata Krishnan, PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects.
“Japanese Notice of Rejection Ground”, Complete English-language translation, mailed May 12, 2009 from JP Patent Office for corresponding JP App. No. 2005-008006.
Japanese Office Action for Japanese Application No. 2005-8006 mailed Nov. 10, 2009. A Partial English-language Translation is Provided.
Hanaoka Yuuji
Haneda Terumasa
Ogawa Yuichi
Takahashi Hidenori
Yoshida Toshiyuki
Baderman Scott
Fujitsu Limited
Fujitsu Patent Center
Truong Loan
LandOfFree
Method of controlling information processing system,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of controlling information processing system,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of controlling information processing system,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4287363