Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
2007-07-24
2007-07-24
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257SE29303, C257S914000, C438S309000, C438S488000
Reexamination Certificate
active
10695336
ABSTRACT:
A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.
REFERENCES:
patent: 4467519 (1984-08-01), Glang et al.
patent: 4559696 (1985-12-01), Anand et al.
patent: 4755476 (1988-07-01), Bohm et al.
patent: 4875085 (1989-10-01), Ueno et al.
patent: 5137839 (1992-08-01), Niitsu
patent: 5150184 (1992-09-01), Eklund
patent: 5242844 (1993-09-01), Hayashi
patent: 5254484 (1993-10-01), Hefner et al.
patent: 5317432 (1994-05-01), Ino
patent: 5323031 (1994-06-01), Shoji et al.
patent: 5360986 (1994-11-01), Candelaria
patent: 5373192 (1994-12-01), Eguchi
patent: 5385863 (1995-01-01), Tatsumi et al.
patent: 5565370 (1996-10-01), Jerome et al.
patent: 5587326 (1996-12-01), Takemura
patent: 5683935 (1997-11-01), Miyamoto et al.
patent: 5708281 (1998-01-01), Morishita
patent: 5744824 (1998-04-01), Kousai et al.
patent: 5893747 (1999-04-01), Yang
patent: 6030874 (2000-02-01), Grider et al.
patent: 6114722 (2000-09-01), Jan et al.
patent: 6294442 (2001-09-01), Kamal
patent: 2002/0145167 (2002-10-01), Yamazaki
patent: 0 521 644 (1993-01-01), None
Carbone et al., “Correlation of Ellipsometric Vol. Fraction to Polysilicon Grain Size from Transmission Electron Microscopy”, Sep. 1999, IEEE/SEMI Adv. Semiconductor Mfg. Conf. and Workshop, pp. 359-367.
Geiss Peter J.
Greco Joseph R.
Kontra Richard S.
Lanning Emily
Doty Heather
International Business Machines - Corporation
Sabo William D.
Schmeiser Olsen & Watts
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