Method of controlling dopant diffusion and metal contamination i

Details Method of controlling dopant diffusion and metal contamination i Method of controlling dopant diffusion and metal contamination i

1996-10-29

1999-07-13

Booth, Richard A.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438585, 257413, H01L 213205, H01L 214763

Patent

active

059239999

ABSTRACT:
A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

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