Method of controlled low-k via etch for Cu interconnections

Details Method of controlled low-k via etch for Cu interconnections Method of controlled low-k via etch for Cu interconnections

2011-03-15

2011-03-15

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S704000, C257SE23145

Reexamination Certificate

active

07906426

ABSTRACT:
An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

REFERENCES:
patent: 2004/0017011 (2004-01-01), Narita et al.
patent: 2005/0079705 (2005-04-01), Takeuchi
patent: 2005/0124149 (2005-06-01), Kim et al.
patent: 2006/0121721 (2006-06-01), Lee et al.
patent: 2006/0252256 (2006-11-01), Weng et al.
patent: 2006/0292856 (2006-12-01), Park et al.
patent: 2007/0020944 (2007-01-01), Chae et al.

Affiliated with

Also associated with

Rating

Method of controlled low-k via etch for Cu interconnections does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of controlled low-k via etch for Cu interconnections, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of controlled low-k via etch for Cu interconnections will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2648709