Method of constructing an integrated circuit memory

Details Method of constructing an integrated circuit memory Method of constructing an integrated circuit memory

1997-07-13

1998-10-06

Niebling, John

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438107, H01L 2118

Patent

active

058175431

ABSTRACT:
A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

REFERENCES:
patent: 3832575 (1974-08-01), Dasgupta et al.
patent: 4074342 (1978-02-01), Honn et al.
patent: 4365284 (1982-12-01), Tanaka
patent: 4525921 (1985-07-01), Carson et al.
patent: 4553050 (1985-11-01), Feinberg et al.
patent: 4622058 (1986-11-01), Leary-Renick et al.
patent: 4646128 (1987-02-01), Carson et al.
patent: 4706166 (1987-11-01), Go
patent: 4714981 (1987-12-01), Gordon
patent: 4841170 (1989-06-01), Eccleston
patent: 4879631 (1989-11-01), Johnson et al.
patent: 4983533 (1991-01-01), Go
patent: 5104820 (1992-04-01), Go et al.
patent: 5107586 (1992-04-01), Eichelberger et al.
patent: 5138437 (1992-08-01), Kumamoto et al.
patent: 5262351 (1993-11-01), Bereau et al.
patent: 5426566 (1995-06-01), Beilstein, Jr. et al.
Garth, "Memory System --An Ultimate in Packaging Technology", Electro 78 Conference, May 1978, pp. 1-2.
Bhatia et al., "Multilayer Glass Ceramic Substrate Design For SS-1 Supercomputer", 43rd Electronic Components and Technology Conference, Jun. 1993, pp. 935-940.

Affiliated with

Also associated with

Rating

Method of constructing an integrated circuit memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of constructing an integrated circuit memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of constructing an integrated circuit memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-76501