Method of configuring memory cell array block, method of...

Details Method of configuring memory cell array block, method of... Method of configuring memory cell array block, method of...

2007-06-05

2007-06-05

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185110

Reexamination Certificate

active

11302606

ABSTRACT:
A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

REFERENCES:
patent: 5572466 (1996-11-01), Sukegawa
patent: 6212121 (2001-04-01), Ryu et al.
patent: 6567307 (2003-05-01), Estakhri
patent: 6590822 (2003-07-01), Hwang et al.
patent: 2002-064142 (2002-02-01), None
patent: 10-2003-0055467 (2003-07-01), None

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