Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-10
2003-04-29
Garrowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06557156
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of field programmable gate arrays (FPGAs) and more particularly to a method of configuring an FPGA using a host processor and a high level language compiler.
2. Description of the Background Art
In recent years, there has been an increasing interest in reconfigurable logic based processing. These systems use dynamically reconfigurable logic, such as FPGAs that can be reconfigured while in use, to implement algorithms directly in hardware, thus increasing performance.
By one count, at least 50 different hardware platforms (e.g., computers) have been built to investigate this novel approach to computation. Unfortunately, software has lagged behind hardware in this area. Most systems today employ traditional circuit design techniques, then interface these circuits to a host computer using standard programming languages.
Work done in high-level language support for reconfigurable logic based computing currently falls into two major approaches. The first approach is to use a traditional programming language in place of a hardware description language. This approach still requires software support on the host processor. The second major approach is compilation of standard programming languages to reconfigurable logic coprocessors. These approaches typically attempt to detect computationally intensive portions of code and map them to the coprocessor. These compilation tools, however, are usually tied to traditional placement and routing back-ends and have relatively slow compilation times. They also provide little or no run-time support for dynamic reconfiguration.
In general, today's tools are based on static circuit design tools originally developed for use in circuit board and integrated circuit design. The full potential of dynamic logic is not supported by such static design tools.
SUMMARY OF THE INVENTION
The method of design for reconfigurable computing (MDRC) of the invention represents a novel approach to hardware/software co-design for reconfigurable logic based coprocessors. A system and method are provided for configuring an FPGA directly from a host processor. It is not necessary to store the configuration data in a file, although it can be so stored if desired. Therefore, this method is particularly suited for use with FPGAs such as reconfigurable coprocessors, which are often reconfigured “on the fly”, i.e., without repowering the FPGA and sometimes while reconfiguring only a portion of the FPGA. A description of the desired functionality for the FPGA is entered using the MDRC libraries and a standard high level language such as Java™. (Java is a trademark of Sun Microsystems, Inc.) Configuration, reconfiguration and host interface software for reconfigurable coprocessors is supported in a single piece of code.
Since MDRC does not make use of the traditional placement and routing approach to circuit synthesis, compilation times are significantly shorter than with prior art methods, being on the order of seconds. This high-speed compilation provides a development environment which closely resembles those used for modern software development.
The MDRC provides a simple alternative to traditional Computer Aided Design (CAD) tool based design. In the preferred embodiment, Java libraries are used to program an FPGA device. This method has the following benefits:
Very fast compilation times. Because standard programming language compilers are used by this approach, compilation is as fast as the host native compiler. With current Java compilers such as Microsoft's J++1.1 compiler compiling over 10,000 lines of code per second, compiling circuits built using MDRC will take on the order of a second to complete. This is in contrast to the hours of turnaround time in existing CAD tools.
Run time parameterization of circuits. Perhaps the most interesting feature of MDRC is its ability to do run-time parameterization of circuits. For instance, a constant adder, using a constant value known only at run-time, can be configured by MDRC during execution. The size of a given component may also be specified dynamically. A 5-bit adder or a 9-bit counter, for instance, can be configured at run-time. This feature has uses in areas such as adaptive filtering.
Object Oriented Hardware Design. Because Java is an object oriented language (i.e., a structured language in which elements are described in terms of objects and the connections between these objects), hardware designed in this language can make use of object-oriented support. Libraries constructed with MDRC may be packaged as objects and manipulated and reused like any standard software component.
Support for dynamic reconfiguration. The ability to dynamically configure a circuit automatically brings with it the ability to do dynamic reconfiguration. Uses for this capability are beginning to appear. For example, a portion of a dynamically reconfigurable FPGA could be configured as a multiplier that multiplies an input value by a constant, the constant being a scaling factor in a signal processing application. Using dynamic reconfiguration, this scaling factor could be changed without interrupting the function of other portions of the configured FPGA.
Standard software development environment. Using a standard programming language (in this case, Java) permits standard software environments to be used by circuit developers. In other words, widely available, off-the-shelf compilers such as Microsoft's J++1.1 compiler could be used to develop circuits to be implemented in an FPGA. This capability has two immediate advantages. First, the user can continue to use whichever tool he or she is already familiar with. Secondly, and perhaps most importantly, FPGA design becomes a software development effort open to programmers. This capability could greatly expand the existing base of FPGA users.
Simplified host interfacing. MDRC requires a host processor to be available for executing the Java code and supplying configuration data to the FPGA. This processor/FPGA combination is a powerful coprocessing environment currently being investigated by researchers. One barrier to use of these systems is the need to interface the FPGA hardware design with the host software design. MDRC merges the software and hardware design activities into a single activity, eliminating these interfacing issues.
Flexibility. Because MDRC comprises a library used by a standard programming language, it may be extended, even by users. This capability provides a level of flexibility unavailable in a static design tool. Users are free to provide new libraries and library elements, or even accessories such as custom graphical user interfaces.
Standard device interface. One way to think of MDRC is not so much as a tool in itself, but as a standard interface to the FPGA device. This interface may be used for FPGA configuration, or it may be used to build other tools. MDRC may even be used as the basis for traditional CAD software such as placement and routing tools. Another way to think of MDRC is as the “assembly language” of the FPGA.
Guaranteed “safe” circuits. MDRC provides an abstraction (a software construct that provides a representation, often simplified, of the hardware) which makes it impossible to produce circuits with contention problems. This makes it impossible when using MDRC to accidentally damage or destroy the device due to a bad configuration. Such protection is highly desirable in a dynamic programming environment like MDRC, where a programming error could otherwise result in permanently damaged hardware. (An incorrectly configured FPGA may inadvertently short power and ground together, destroying the device.) A side effect of this feature is that the MDRC may be used as an implementation vehicle for the emerging field of genetic algorithms.
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Bever Hoffman & Harms
Cartier Lois D.
Garrowski Leigh M.
Stephenson Julie
Xilinx , Inc.
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