Method of configuring an integrated circuit

Details Method of configuring an integrated circuit Method of configuring an integrated circuit

1978-08-07

1980-11-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365174, 307238, G11C 1140

Patent

active

042336740

ABSTRACT:
In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

REFERENCES:
patent: 3813650 (1974-05-01), Hunter
patent: 3940740 (1976-02-01), Coontz

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