Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-23
2006-05-23
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07051314
ABSTRACT:
A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from exposure of a unit area to a beam of radiation, are additionally stored in the library. These delay time values are detected by successively exposing unit areas of a test wafer to a beam of radiation as a function of relative positions of each integrated circuit chip within the unit exposure area. In a modified embodiment, only one integrated circuit chip within each unit area is exposed to the radiation beam, and the exposure-dependent delay time values are detected as a function of position within the exposed integrated circuit chip or as a function of distance from the center of the each unit area.
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McGinn IP Law Group PLLC
NEC Electronics Corporation
Rossoshek Helen
Thompson A. M.
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