Method of CMOS source/drain extension with the PMOS implant...

Details Method of CMOS source/drain extension with the PMOS implant... Method of CMOS source/drain extension with the PMOS implant...

2002-07-18

2004-05-18

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S199000, C438S229000, C438S231000

Reexamination Certificate

active

06737354

ABSTRACT:

FIELD OF THE INVENTION
This invention focuses on the improvement of source/drain extension fabrication process in Complementary Metal Oxide Semiconductor (CMOS) devices.
BACKGROUND OF THE INVENTION
Complementary Metal Oxide Semiconductor (CMOS) devices have found wide use in the electronics industry. These devices include both NMOS and PMOS transistors to form the logic elements. These devices have source/drain MDD (Medium Doped Drain) extension implants. These extension implants may also be High Doped Drain (HDD) implants. The devices may include on the same wafer both low voltage (LV) and high voltage (HV) MOS transistors. For example see Hutter et al. U.S. Pat. No. 5,472,887, incorporated herein by reference. More on fabrication according to the prior art is found in the text edited by S. M. Sze entitled “VLSI Technology Second Edition” published by Mc Graw Hill.
Referring to
FIG. 1
there is illustrated the conventional CMOS source/drain MDD extension process. The gate electrode is defined by growing a thin silicon dioxide layer over the silicon base and then the deposition of a polysilicon film (2000 Angstroms for example) over the wafer. The wafer is then patterned and etched forming the gate electrode as represented by stage
101
. The second stage
102
is a growth of a poly oxide film covering the entire wafer. The next step
103
is NMOS MDD implant of high voltage NMOS transistors (NMDD
2
+). The implant is annealed with heat diffusing the implant under the poly oxide in the silicon base. A photoresist is placed to protect the NMOS transistor areas leaving open the PMOS areas. This is represented by stage
104
.
The next step is to implant the area that defines the core PMOS transistors. PMOS MDD implant is then performed as represented by stage
105
with the implant under the poly oxide grown in stage
102
on the silicon base on either side of the gate. The PMOS transistor regions are then covered with a photoresist to protect from the low voltage NMOS implant in stage
107
. This is represented by stage
106
. Stage
107
illustrates the low voltage NMOS MDD implant. After the NMOS MDD implant the wafer is annealed as represented by stage
107
. This is then covered with a photoresist as represented by stage
108
.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention a better MDD and/or HDD extension implant procedure to achieve higher dose activation, shallow, and more abrupt junctions is provided by processing steps that provide a side wall spacer from the gate before PMOS implant.
In accordance with another embodiment of the present invention, processing steps are adjusted to provide a cap oxide after an NMOS implant to prevent the implant from out diffusing from the silicon and provide side wall spacer form PMOS implant.
In accordance with another embodiment of the present invention including implanting NMOS area directly on either side of the gates without an oxide layer then deposit cap ox layer followed by dry etching PMOS device areas with a dry etch to remove cap oxide from the silicon base but leaving cap oxide on the side walls before implanting the PMOS device areas.


REFERENCES:
patent: 2001110913 (2001-04-01), None
patent: 2001110913 (2001-04-01), None
Wolf S., Silicon Processing, 1995, Lattice Press, vol. 3, pp. 595-597.

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