Method of clock routing for semiconductor chips

Details Method of clock routing for semiconductor chips Method of clock routing for semiconductor chips

1997-09-22

1999-12-21

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

713503, G06F 1500

Patent

active

060060255

ABSTRACT:
A method of wire routing includes the steps of providing an array of cells on a semiconductor chip, determining a minimum distance location between a first clock point, an second clock point and a drive point for connecting to a connection point in the array of cells, and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create a path for a wire for connecting the first clock point and the second clock point to a connection point such that skew is minimized between the starting clock point and the second clock point from the connection point when a clock signal is provided to the connection point from the drive point.

REFERENCES:
patent: 5410491 (1995-04-01), Minami
patent: 5784600 (1999-07-01), Doreswamy et al.
patent: 5838581 (1998-11-01), Kuroda
patent: 5849610 (1998-12-01), Zlu

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