Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
1999-07-14
2001-04-24
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
C438S691000, C438S672000, C438S711000
Reexamination Certificate
active
06221772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a method of cleaning away polymer, and more particularly, to a method of cleaning polymer inside contact holes on a semiconductor wafer.
2. Description of the prior art
The inter-layer dielectric (ILD) positioned between the MOS transistor and the metallic conductive layer on the semiconductor wafer isolates and protects devices of the semiconductor wafer. A contact plug positioned within the ILD is employed as an electrical terminal between the MOS transistor and the metallic conductive layer. The contact plug is formed through etching a contact hole onto the ILD then filling the hole with metallic material.
In semiconductor processing at widths less than 0.25 um, a borderless contact structure is generally used to allow shorter distance between the contact hole and border of each layer so as to increase the device density on the semiconductor wafer. The borderless contact structure according to the prior art comprises a silicon nitride layer employed as a stop-etching layer positioned between the ILD and the MOS transistor. The ILD is made of silicon oxide and positioned above the MOS transistor. Because etching stops at the silicon nitride layer during processing of the borderless contact holes, etching of oxide layer in shallow trench isolation (STI) is prevented on the part of the MOS transistor.
Please refer to FIG.
1
.
FIG. 1
is a structural schematic diagram of the borderless contact holes
24
,
26
on the semiconductor wafer
10
according to the prior art. The semiconductor wafer
10
comprises a substrate
12
, a MOS transistor
14
, a shallow trench
16
, a silicon nitride layer
18
, a silicon oxide layer
20
and two borderless contact holes
24
,
26
. The MOS transistor
14
and the shallow trench
16
are both positioned on the substrate
12
. The silicon nitride layer
18
is positioned on the MOS transistor
14
. The silicon oxide layer
20
is deposited on the silicon nitride layer
18
.
Please refer to
FIG. 2
to FIG.
4
.
FIG. 2
to
FIG. 4
are schematic diagrams of forming the borderless contact holes
26
as shown in FIG.
1
. As shown in
FIG. 2
, the nitride layer
18
and the silicon oxide layer
20
are sequentially deposited on the substrate
12
. Then, a photo-resist layer
22
is formed in a predetermined area of the silicon oxide layer
20
. Next, the position of the borderless contact hole
26
is defined by using the pattern transfer of a photomask. Next, as shown in
FIG. 3
, an anisotropic dry-etching process is performed on the portion of the silicon oxide layer
20
not covered by the photo-resist layer
22
to form an opening
28
by removing the silicon oxide layer
20
down to the silicon nitride layer
18
. This dry-etching process employs fluorocarbon (C
4
F
8
) and argon (Ar) as reacting gases and adds carbon monoxide (CO) to the reacting gases for adjusting the ratio of fluorine atoms to carbon atoms (F/C). Finally, as shown in
FIG. 4
, an etching process is performed on the silicon nitride layer
18
and a removing process is performed on the photo-resist layer
22
respectively. This completes processing of the borderless contact holes.
After dry-etching of the silicon nitride layer
18
, polymers remain on the side and the bottom surface of the borderless contact hole
26
leading to a smaller contact area between the borderless contact hole
26
and the source and drain of the MOS transistor
14
. The polymers on the bottom side of each contact hole
26
,
28
also affect the surface condition and bonding of the metal layer in subsequent metallization processes. Therefore, the contact plug subsequently formed by filling metallic material in the contact hole
26
through metallic sputtering has a high resistance in excess of 5 ohms. In order to prevent increases of the resistance of the contact plug, the polymer remaining in the borderless contact hole
26
after the borderless contact hole
26
need to be completed cleaned out.
After dry-etching to form the opening in the region not covered by the photo-resist layer
22
, polymer containing carbon atom is also generated from the etched silicon oxide that remain on the side of the opening
28
and the surface of the silicon nitride layer
18
. These polymers affect the subsequent dry-etching process on the silicon nitride layer
18
as well as the after etching inspection critical dimension (AEI CD) of the borderless contact hole
26
. Furthermore, the source or drain of the MOS transistor
14
may contain leftover polymer so as to form defects during the dry-etching process on the silicon nitride layer
18
. However, if the polymers remaining within the opening
28
are removed at the same time the dry-etching process on the silicon nitride layer is performed, the etching selective ratio of silicon oxide to silicon nitride will be decreased during the dry-etching process. Thus, it is difficult to stop etching the silicon nitride layer
18
at the right time.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of in-situ cleaning the polymer from holes on a semiconductor wafer and in-situ remove the silicon nitride layer, to solve those problems generated from forming a borderless contact hole.
In a preferred embodiment, the present invention provides a method of in-situ cleaning polymers in holes and in-situ remove the silicon nitride layer on a semiconductor wafer; the semiconductor wafer comprising a substrate, a silicon nitride (Si
3
N
4
) layer on the substrate, a silicon oxide (SiO
2
) layer on the silicon nitride layer, and a photo-resist layer on the silicon oxide layer; the silicon oxide layer and the photo-resist layer having a hole extending down to the silicon nitride layer, the hole containing polymer left by etching of the silicon oxide layer, the method comprising:
performing a in-situ plasma ashing process by injecting oxygen (O
2
) and argon (Ar) to completely remove the photo-resist layer and the polymer remaining within the hole, the flow rate of O
2
being maintained between 50~2000 sccm (standard cubic centimeter per minute) and the flow rate of Ar being maintained between 50~500 sccm.
It is an advantage of the present invention that using the method of in-situ cleaning the polymers from within the holes, the polymer remaining within the holes may be cleaned out to form a borderless contact hole with an unbroken outline. This is helpful to increase the yield of semiconductor products.
This and other objective of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5895239 (1999-04-01), Jeng et al.
Chen Tong-Yu
Huang Wei-Che
Yang Chan-Lon
Hsu Winston
Huynh Yennhu B.
Nguyen Tuan H.
United Microelectronics Corp.
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