Method of circuit power tuning through post-process flattening

Details Method of circuit power tuning through post-process flattening Method of circuit power tuning through post-process flattening

2011-02-01

2011-02-01

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S013000

Reexamination Certificate

active

07882460

ABSTRACT:
A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first optimization is subject to a first constraint that all instances of the at least one reused cell are kept identical. The at least one reused cell is uniquified. A second optimization is performed to meet a second objective allowing uniquified instances of the at least one reused cell to be independently modified. The second optimization is subject to a second constraint that the first objective remains met.

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