Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-08-10
2001-11-20
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185160, C365S185270, C365S185280
Reexamination Certificate
active
06320789
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of Chisel (CHannel Initiated Secondary ELectron) programming in non-volatile memory by source bias.
2. Description of the Related Art
In the last decade, flash non-volatile memory technologies have advanced substantially. Many array architecture and program/erase methodologies have been proposed to enable manufacturing of high speed and high density flash products. Recently, Chisel (CHannel Initiated Secondary ELectron) programming has attracted considerable attention because of its numerous advantages relative to competing methodologies. One of the primary advantages offered by Chisel programming is V
th
control which is absent in CHE (Channel Hot Electron) programming. With Chisel programming, non-volatile memory cells are rapidly programmed until they turn themselves off. Programmed code then saturates abruptly to V
th
which is regulated by control gate voltage. This allows Chisel programming to be used to correct over-erased bits, to operate without programming verification and is suitable for multilevel flash. Another advantage of Chisel programming is it requires less programming current/power to attain the same programming speed enabled by CHE making Chisel more suitable for low power applications. Moreover, it uses a back gate bias to resolve punch through and drain-coupled turn-on problems encountered when scaling CHE cells.
FIG. 1
is a diagram of a non-volatile memory cell, which is used to demonstrate conventional Chisel programming technique. The non-volatile memory cell is comprised of a P-substrate (P
sub
) a deep N-well (DNW), a P-well (PW), a floating gate (FG), a control gate (CG), a N
+
doped region D serving as a drain, a N
+
doped region S serving as a source, a P
+
doped region B serving as a body, and four bias terminals V
g
, V
d
, V
b
and V
s
.
Table 1 lists the bias of Chisel programming in non-volatile memory cells. In Table 1, V
dp
, V
gp
, V
sp
and V
bp
represent drain programming voltage, gate programming voltage, source programming voltage and body programming voltage respectively. V
dr
, V
gr
, V
sr
and V
br
represent drain reading voltage, gate reading voltage, source reading voltage and body reading voltage respectively. When programming is proceeding, a back-gate bias less than zero is needed, e.g., V
bp
−V
sp
=−2~−3 V. When reading is proceeding, V
br
is equal to zero.
TABLE 1
Drain bias
Gate bias
Source bias
Body bias
pro-
V
dp
= 3.3 V
V
gp
= 5 V
V
sp
= 0 V
V
bp
= −2~−3 V
gram-
ming
reading
V
dr
= 1.2~1.5 V
V
gr
= 3.3 V
V
sr
= 0 V
V
br
= 0 V
Despite Chisel programming's above-mentioned advantages, it still fails to overcome a number of problems. Because the difference between V
bp
and V
br
is 2~3 V, when switching the programming and reading biases while changing the potential of P-well (PW), both the parasitic capacitor (C
1
) which exists between source S and the P-well (PW) as well as the parasitic capacitor (C
2
) residing between the P-well (PW) and the P-substrate (P
sub
) are charged. Even more problematic is that the parasitic capacitor (C
2
) existing between the P-well (PW) and the P-substrate (P
sub
) is relatively large while the power generated by the charging pump circuit is limited. Therefore, a relatively long charging time is required thereby reducing the switching speed between programming and reading biases.
As mentioned previously, there is no need for Chisel programming in non-volatile memory to execute programming verify. Nevertheless, proceeding with programming verify can enhance programming speed. Hence, adding the programming verify step in Chisel programming is beneficial to the enhancement of the programming speed. However, in practical terms, the switching speed between programming and reading is too slow to utilize programming verify. Moreover, the source disturbance phenomenon becomes worse with an increased number of devices as the hot carrier destroys the tunnel oxide layer thus reducing reliability of the device.
SUMMARY OF THE INVENTION
To resolve the above-mentioned problems, the invention provides a method of programming in non-volatile memory by source bias which prevents the negative effects of parasitic capacitors, simplifies the bias voltage circuit, enhances reliability of devices, and reduces disturbance.
The present invention provides a method of programming in non-volatile memory by source bias wherein during reading and programming operations, a substrate reading voltage and a substrate programming voltage are used to off-set the negative effects discussed above. The method is comprised of the following steps: changing the substrate programming voltage to reduce the difference between substrate programming voltage and substrate reading voltage thereby allowing the programming operation using the changed substrate programming voltage.
According to the embodiment of the invention, the changed body programming voltage is equal to the body reading voltage. Accordingly, the invention changes the biases needed in programming operations. By aligning body programming voltage and the body reading voltage, the negative effect produced by the parasitic capacitor in memory cells is alleviated, device reliability is enhanced and source disturbance is reduced.
REFERENCES:
patent: 5341342 (1994-08-01), Brahmbhatt
patent: 5659504 (1997-08-01), Bude et al.
patent: 6002610 (1999-12-01), Cong et al.
Chen Bin-Shing
Chen Yimin
Dinh Son T.
Ladas & Parry
Winbond Electronics Corp.
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