Method of chemically mechanically polishing an electronic compon

Details Method of chemically mechanically polishing an electronic compon Method of chemically mechanically polishing an electronic compon

1995-11-14

1999-03-23

Breneman, R. Bruce

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438697, 252 791, H01L 21461

Patent

active

058858997

ABSTRACT:
A method of forming interlevel studs in an insulating layer on a semiconductor wafer. First, a conformal BPSG layer is formed on a Front End of the Line (FEOL) semiconductor structure. Vias are opened through the BPSG layer to the FEOL structure. A layer of poly is formed (deposited) on the BPSG layer, filling the vias. The poly layer may be insitu doped poly or implanted after it is deposited. The wafer is annealed to diffuse dopant from the poly to form diffusions wherever the poly contacts the substrate. A non-selective slurry of colloidal silica and at least 1% ammonium hydroxide is used to chem-mech polish the poly from the BPSG layer and, simultaneously, planarize the BPSG layer.

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NL8200782, Abstract Only, "Planarising the Surface of Semiconductor Bodies With Grooves".

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