Method of chemical modification of structure topography

Details Method of chemical modification of structure topography Method of chemical modification of structure topography

2001-12-03

2004-09-21

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

Reexamination Certificate

active

06794290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods of thin film deposition and, more specifically, to a method of minimizing structure overhang during the process of filling high aspect ratio gaps on substrates.
2. Background of the Invention
As semiconductor technology advances, circuit elements and interconnections on wafers or silicon substrates become increasingly more dense. In order to prevent unwanted interactions between these circuit elements, insulator-filled gaps or trenches located therebetween are provided to physically and electrically isolate the elements and conductive lines. However, as circuit densities continue to increase, the widths of these gaps decrease, thereby increasing gap aspect ratios, typically defined as the gap height divided by the gap width. As a result, filling these narrower gaps becomes more difficult, which can lead to unwanted voids and discontinuities in the insulating or gap-fill material.
In previous generations of microelectronic devices the gaps between metal lines were filled using either PECVD (plasma enhanced chemical vapor deposition) processes or the combinations of those with sputter etch steps. For example, U.S. Pat. No. 5,270,264 to Andideh et al. describes a gap-filling process which involves the steps of deposition by PECVD, followed by argon sputter etching, followed by another PECVD deposition step, i.e., a PECVD “dep-etch-dep” process. The article by S. Pennington et al. (hereinafter “the article by Pennington et al.”), entitled “An Improved Interlevel Dielectric Process for Submicron Double-Level Metal Products,” in
Proceedings of the
6
th
International IEEE VLSI Multilevel Interconnection Conference
, (1989), pp. 355-359, describes a dielectric gap-filling process using both PECVD and thermal CVD (THCVD). The article by D. Cote et al. (hereinafter “the article by Cote et al.”), entitled “Low-Temperature Chemical Vapor Deposition Processes and Dielectrics for Microelectronic Circuit Manufacturing at IBM”, in the
IBM Journal of Research and Development
, vol. 39, no. 4, (July 1995), pp. 437-464, describes several known CVD processes, including low pressure (LP), atmospheric pressure (AP) CVD, and plasma-enhanced (PE) CVD, which are background to the present invention. However, the gap-fill capabilities of such processes or combinations of processes do not extend beyond aspect ratios of 1.3:1 at spacing 0.45 &mgr;m or 4500 Å, even when “dep-etch-dep” cycles are performed, as described in U.S. Pat. No. 5,270,264 and the article by Cote et al. Specifically, the article by Cote et al. refers to and presents data demonstrating the inability of PECVD processes to satisfy the gap-fill requirements of advanced microelectronic devices with either undoped or doped silica glass.
In the gap-fill process described in U.S. Pat. No. 5,270,264, a step of deposition by PECVD is followed by a sputter etch step with argon and another step of deposition by PECVD. As understood by those skilled in the art, deposition by PECVD is strictly a deposition step, i.e., not involving simultaneous etching during exposure to the depositing plasma. U.S. Pat. No. 5,270,264 describes a gap-filling process which performs a sputter etch using inert gases of heavy atomic weight such as Ar, Kr, and Xe. The process parameters for the PECVD deposition and etching are specified in that patent for the plasma power density and pressure. In addition, the capabilities of the dep-etch-dep processes described in the articles by Pennington et al., by Cote et al., and U.S. Pat. No. 5,270,264 are limited by virtue of the use of PECVD deposition, the selection of sputter gases described therein, and the process parameters defined for the sputter etch step. As a result, the processes described in these references cannot be used to fill gaps having aspect ratios greater than about 2:1 and width less than about 0.65 &mgr;m (6500 Å).
High density plasma (HDP) chemical vapor deposition (CVD) processes are currently used to fill gaps having aspect ratios of about 3:1 and having close spacing, e.g. about 0.25 &mgr;m. HDP processes operate at a pressure regime several (e.g., two to three) orders of magnitude lower than that of their PECVD counterparts. Moreover, in an HDP reactor, power is coupled inductively to the plasma, resulting in higher plasma density. Consequently, in an HDP reactor, because of the pressure and plasma characteristics, the species impinging on the depositing film surface are much more energetic than in a PECVD reactor, such that gas-solid collisions may result in sputtering of the deposited film. In an HDP CVD deposition process, the sputter etch component is typically between 10% and 20% of the net deposition rate. Another characteristic of HDP deposition is that increased bias power applied to the wafer results in an increased in-situ sputter etch component, thereby decreasing the deposition rate.
By contrast, in PECVD reactors the coupling is capacitive, resulting in much lower plasma density. The combination of low plasma density and high pressure results in negligible film sputtering in PECVD deposition. In addition, those skilled in the art will understand that the rate of film deposition in PECVD processes may increase with the amount of bias power applied to the wafer.
The differences in the physics and chemistry of PECVD and HDP processes result in significant differences in the growth of the deposited film. In PECVD processes, plasma is used to generate deposition precursors, which in turn, are driven to the wafer surface by applied bias to the wafer. Because of the relatively high pressure of operation (on the order of 1 Torr), the ions experience a large number of collisions as they cross the sheath. As a result, the flux of deposition precursor species to the wafer surface is distributed. Moreover, the mixture is depleted of deposition precursors as it diffuses towards the bottom of the trench, and, as a result, the net rate of film growth at the bottom of the trench is smaller than that at the entry region of the trench. Therefore, void-free filling of gaps having high aspect ratios (i.e., aspect ratios approaching or exceeding 2:1 at 0.65 &mgr;m spacing) cannot be achieved using PECVD methods since the opening to the gap will be closed long before the gap is filled. For these reasons, the process sequence described in U.S. Pat. No. 5,270,264 of PECVD deposition, argon sputter etch, followed by another PECVD deposition, cannot provide void-free filling of high aspect ratio gaps at current microelectronic dimensions.
Existing HDP deposition processes typically employ chemical vapor deposition (CVD) with a gas mixture containing oxygen, silane, and inert gases, such as argon, to achieve simultaneous dielectric etching and deposition. In an HDP process, RF bias is applied to a wafer substrate in a reaction chamber. As a result, the flux of deposition precursors is perpendicular to the wafer, and the net film growth occurs perpendicularly to the bottom of the feature. Some of the gas molecules (particularly argon) are ionized in the plasma and accelerate toward the wafer surface when the RF bias is applied to the substrate. Material is thereby sputtered when the ions strike the surface. As a result, dielectric material deposited on the wafer surface is simultaneously sputter-etched to help keep gaps open during the deposition process, which allows higher aspect ratio gaps to be filled.
FIGS. 1A-1D
illustrate, in more detail, the simultaneous etch and deposition (etch-dep) process described above. In
FIG. 1A
, a gas mixture of silane (SiH
4
), oxygen (O
2
), and an inert gas such as argon (Ar) begins depositing SiO
2
on the surface of a wafer
100
for filling a gap
110
between circuit elements
120
. As SiO
2
, formed from the SiH
4
and O
2
, is being deposited, charged Ar and other charged ions impinge on the SiO
2
or dielectric layer
125
, thereby simultaneously etching the SiO
2
layer. However, because the etch rate at about 45° is approximately three to four time

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