Method of chemical-mechanical polishing

Details Method of chemical-mechanical polishing Method of chemical-mechanical polishing

1999-03-02

2001-01-09

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Utilizing reflow

C438S692000, C438S691000

Reexamination Certificate

active

06171976

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88100969, filed Jan. 22, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a planarizing process. More particularly, the present invention relates to a method of chemical-mechanical polishing in which a dummy pattern is used.
2. Description of the Related Art
Chemical-mechanical polishing is currently the only technique capable of providing global planarization in VLSI process, and even in ULSI process.
FIG. 1
is a schematic, top view diagram of a conventional wafer.
FIGS. 2A and 2B
are schematic, cross-sectional diagrams of
FIG. 1
along a line II—II, which are used to depict steps in a chemical-mechanical polishing process.
Referring to
FIGS. 1 and 2A
, a die region
102
and a scribe line region
104
are defined on a wafer
100
. A width of the scribe line is 110 &mgr;m. A metal layer
106
is formed on the die region
102
. A silicon dioxide layer
108
is formed to cover the wafer
100
and the metal layer
106
by chemical vapor deposition.
Referring to
FIG. 2B
, the silicon dioxide layer
108
is planarized by chemical-mechanical polishing.
As shown in
FIGS. 2A and 2B
, the height difference between the scribe line region
104
and the die region
102
is large because the metal layer
106
is formed on the die region
102
and nothing besides test keys is formed in the scribe line region
104
, thus the surface of the silicon dioxide layer
108
is not formed flat. As a result, a part of the silicon dioxide layer
108
formed on the scribe line region
104
is easily polished in the chemical-mechanical polishing process, especially at an intersection between scribe lines. Therefore the uniformity of the silicon dioxide layer
108
is poor and a dishing effect occurs. Devices at a corner of the die region
102
are easily abraded.
FIGS. 3A and 3B
are schematic, cross-sectional diagrams of
FIG. 1
along a line II—II, which are used to depict steps in another chemical-mechanical polishing process.
Referring to
FIG. 3A
, a borophosphosilicate glass layer
110
is formed to cover the metal layer
106
and the wafer
100
. A silicon dioxide layer
108
is formed on the borophosphosilicate glass layer
110
.
Referring to
FIG. 3B
, the silicon dioxide layer
108
is planarized by chemical-mechanical polishing.
Although the borophosphosilicate glass layer
110
is formed to reduce the height difference between the die region
102
and the scribe line region
104
, it has little effect. The dishing effect also occurs.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of chemical-mechanical polishing in which a dummy pattern that avoids a dishing effect is used.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of chemical-mechanical polishing in which a dummy pattern is used. A die region and a scribe line region are defined on a wafer. A dummy pattern is formed in the scribe line region. A dielectric layer is formed to cover the dummy pattern and the wafer. The dielectric layer is planarized by chemical-mechanical polishing.
By using the dummy pattern, the surface of the dielectric layer is flat when formed. As a result, the uniformity of the chemical-mechanical polishing process is improved and the dishing effect is avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
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patent: 5362669 (1994-11-01), Boyd et al.
patent: 5602423 (1997-02-01), Jain
patent: 5670410 (1997-09-01), Pan
patent: 5698892 (1997-12-01), Koizumi et al.
patent: 5760484 (1998-06-01), Lee et al.
patent: 5930646 (1999-07-01), Gerung et al.
patent: 9-8039 (1997-01-01), None

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