Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-08-14
2002-04-16
Baderman, Scott (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S044000, C703S025000
Reexamination Certificate
active
06374372
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for METHOD OF CHECKING PARALLEL PORT OF PERSONAL COMPUTER USING LOOPBACK earlier filed in the Korean Industrial Property Office on Sep. 4, 1997 and there duly assigned Serial No. 45817/1997.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method of checking a parallel port during production of a personal computer and more particularly, to a method of checking a parallel port using a loopback technique, and to a loopback connector used for the same.
2. Related Art
Typically, a personal computer includes one parallel port and two serial ports, these ports being arranged on a rear of the computer. When a printer is connected to the parallel port, the personal computer transmits control signals for controlling the printer and data signals representing information to be printed, and receives status signals from the printer, through the parallel port.
Once a personal computer is in the final stages of manufacture, it is necessary to test the parallel port of the personal computer. To do so, a printer is usually connected to the parallel port and a test signal is transmitted to the printer from the personal computer. The status of the printer is then checked to test the operation of the parallel port.
The above method of testing the parallel port of a computer is complicated and time consuming. In addition, it requires a relatively large test space.
Therefore, there is a need for the development of a method for simply and effectively checking the parallel port of a personal computer. There is also a need for the development of a loopback connector which can be used for checking the parallel port.
The following patents are considered to be representative of the prior art, and are burdened by the disadvantages set forth herein: U.S. Pat. No. 5,161,162 to Watkins et al., entitled Method And Apparatus For System Bus Testability Through Loopback, U.S. Pat. No. 5,193,093 to Okazaki, entitled Data Transfer Process With Loop Checking, U.S. Pat. No. 5,247,690 to Fain, entitled Method For Detecting Transmitting Control Code Using M Out Of N Detection Scheme For Initiating A Latching Loopback Test Procedure, U.S. Pat. No. 5,265,089 to Yonehara, entitled Loopback Test Circuit, U.S. Pat. No. 5,357,519 to Martin et al., entitled Diagnostic System, U.S. Pat. No. 5,539,917 to Jirgal, entitled Computer System Having Circuit Interfacing A DMA Controller Directly With A Parallel Port Having Specific Timing Control To Allow Printing Operation Without Microprocessor Intervention, U.S. Pat. No. 5,557,741 to Jones, entitled Test Apparatus And Method For A Computer Parallel Port, U.S. Pat. No. 5,586,123 to Baker, entitled Interface And Loopback Circuit For Character Based Computer Peripheral Devices, U.S. Pat. No. 5,588,114 to Bhatia, entitled Method And Apparatus For Passive Loopback Testing Of Software-Controllable Parallel Ports, U.S. Pat. No. 5,592,615 to Mishima, entitled Malfunctioning Parts Detecting Device And A Method Of Detecting Malfunctioning Parts, U.S. Pat. No. 5,636,348 to Buxton et al., entitled Control System For A Multiple Mode Standard Parallel Port For A Personal Computer, U.S. Pat. No. 5,694,557 to Yang, entitled Time Multiplexing Address And Data On An Existing PC Parallel Port, and U.S. Pat. No. 5,754,881 to Aas, entitled Method Of Controlling A PC Parallel Port Switch For Connecting Multiple Peripherals To The Same Parallel Port.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provide a method of simply and effectively checking the parallel port of a personal computer.
It is a second object of the present invention to provide a loopback connector for checking the parallel port.
Accordingly, to achieve the first object of the present invention, a method of checking a parallel port of a personal computer includes the steps of: loopback-connecting pins, corresponding to control signals and data signals transmitted to a printer, to pins corresponding to status signals transmitted to the computer; checking whether there is a parallel port, and stopping the checking if there is no parallel port; generating the control signals and reading looped-back status signals after a predetermined time to check control pins; and generating the data signals and reading looped-back status signals after a predetermined time to check data pins.
To accomplish the second object of the present invention, a loopback connector includes: a port connection portion for plugging into a parallel port of a personal computer; a pin interconnection portion, including 25 pins and a cover, for protecting the port connection portion and the pin interconnection portion, wherein a first pin is connected to a thirteenth pin, a tenth pin is connected to a sixteenth pin, an eleventh pin is connected to a seventeenth pin, a twelfth pin is connected to a fourteenth pin, and second through ninth pins are all together connected to a fifteenth pin.
REFERENCES:
patent: 5161162 (1992-11-01), Watkins et al.
patent: 5193093 (1993-03-01), Okazaki
patent: 5247690 (1993-09-01), Fain
patent: 5265089 (1993-11-01), Yonehara
patent: 5357519 (1994-10-01), Martin et al.
patent: 5539917 (1996-07-01), Jirgal
patent: 5557741 (1996-09-01), Jones
patent: 5586123 (1996-12-01), Baker
patent: 5588114 (1996-12-01), Bhatia
patent: 5592615 (1997-01-01), Mishima
patent: 5636348 (1997-06-01), Buxton et al.
patent: 5694557 (1997-12-01), Yang
patent: 5754881 (1998-05-01), Aas
IBM Tech. Disc. Bull., “Printer Port Check Point Card”, vol. No. 34, issue No. 7A, pp. 285-286, Dec. 1991.
Baderman Scott
Bushnell , Esq. Robert E.
Sam-Sung Electronics Co., Ltd.
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