Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-20
2003-02-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06519758
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of checking exposure patterns formed over a photo-mask, and more particularly to a method of checking exposure patterns formed over a photo-mask, wherein data of a layout-designed mask pattern are used to carry out plural electron beam exposures to a single photo-mask in order to form mask patterns over the single photo-mask.
A photolithography technique is used for manufacturing the semiconductor integrated circuit. The photolithography technique utilizes a photo-mask. This photo-mask comprises a transparent substrate such as a glass substrate with a light-shielding mask pattern of a metal such as chromium. This mask pattern is formed by an electron beam lithography technique which uses an electron beam exposure system. Layout designed data are obtained from design data of semiconductor integrated circuits. The layout design data are used as pattern data to enable the electron beam exposure system to carry out an electron beam exposure. The pattern data comprise combinations of plural rectangle-shaped patterns which represent elements of the semiconductor integrated circuits, for example, gate electrode regions, and source and drain regions. In the photolithography process for forming the mask pattern, a pattern is projected with shrinkage onto a photo-mask, wherein a rate of shrinkage is usually ⅕.
In accordance with the layout design, layout data representing fundamental devices such as transistors have previously been prepared, and combinations thereof are laid-out. Plural layout data are laid-out, and data inter-connecting those layout data are converted into exposure data for the electron beam exposure system.
The prepared layout data are classified into first type layout data for traditional process and second type layout data for advanced process. In order to effectively utilize the first type layout data for traditional process, the exposure data are also divided into first type electron beam exposure data for the traditional process and second type electron beam exposure data for the advanced process, so that plural time exposure processes are carried out for the single photo-mask.
If it is required to convert data of large capacity and high integration for a single chip into the electron beam exposure data, or if it is required to synthesize those data, it might be difficult to process the data due to the limited throughput and the limited capacity of the storage medium. In this case, it is effective that those large capacity and high integration data are divided into plural modules before each module is then converted into the electron beam exposure data. Plural sets of the electron beam exposure data are used for carrying out plural time exposure processes for the single photo-mask.
The junction portions of the different mask patterns are double-exposed. A countermeasure is made to prevent any formation of a slit due to miss-alignment of the plural time exposures.
Namely, if the single photo-mask is subjected to the plural time exposures based on the plural sets of the electron beam exposure data to form the mask pattern, then junction portions or overlapping regions of the different mask patterns are double-exposed. The adjacent mask patterns are aligned so that the adjacent mask patterns have overlapping regions to each other. These overlapping regions receive electron beam exposures two times. If a negative resist is used, a light-shielding mask pattern is widen in the junction regions or the overlapping regions. If a positive resist is used, a light-shielding mask pattern is narrowed in the junction regions or the overlapping regions.
FIG. 1A
is a fragmentary plane view illustrative of a photo-mask of a negative resist type having received separate exposures of a first mask pattern “A” and a second mask pattern “B”. The junction regions or the overlapping regions between the first and second mask patterns “A” and “B” are defined between a continuously broken line and a discontinuously broken line. First, second, third and fourth interconnections
401
,
402
,
403
and
404
extend across the junction regions or the overlapping regions defined between the continuously broken line and the discontinuously broken line. Across portions of the first, second, third and fourth interconnections
401
,
402
,
403
and
404
receive double exposures, for which reason the across portions of the first, second, third and fourth interconnections
401
,
402
,
403
and
404
increase in width due to the photo-mask of the negative type resist.
FIG. 1B
is a fragmentary plane view illustrative of a photo-mask of a positive resist type having received separate exposures of a first mask pattern “A” and a second mask pattern “B”. The junction regions or the overlapping regions between the first and second mask patterns “A” and “B” are defined between a continuously broken line and a discontinuously broken line. First, second, third and fourth interconnections
401
,
402
,
403
and
404
extend across the junction regions or the overlapping regions defined between the continuously broken line and the discontinuously broken line. Across portions of the first, second, third and fourth interconnections
401
,
402
,
403
and
404
receive double exposures, for which reason the across portions of the first, second, third and fourth interconnections
401
,
402
,
403
and
404
decrease in width due to the photo-mask of the positive type resist.
If the plural times exposures of plural patterns to the single photo-mask are carried out, it is necessary to check whether or not the plural patterns are formed without miss-alignment. For example, it is verified that the patterns formed on the photo-mask are identical with checking-purpose data prepared from the layout data. The double-exposed parts of the interconnections are made wider or narrower than the intended width defined by the checking data. For this reason, it is difficult that the mask patterns over the photo-mask exactly correspond to the checking data.
Even the shapes of the light-shielding mask patterns over the photo-mask are different from the checking data, if the difference is in the acceptable range which is calculated in accordance with the defective regulation in the processes, then the checker verifies that the mask patterns are not defective. Namely, the upper limit of the number of errors is set in accordance with the defective regulation for enabling the checker to verify that the mask patterns are not defective. As described above, the double-exposed parts of the interconnections are wider or narrower, for which reason the double-exposed parts are likely to be beyond the upper limit, and thus the checker verifies that the mask patterns are defective. Once the checker verifies that the mask patterns are defective, then the checker discontinues the current checking operation.
In the above circumstances, it had been required to develop a novel method of checking mask patterns over a photo-mask free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel method of checking mask patterns free from the above problems.
It is a further object of the present invention to provide a novel method of checking mask patterns, wherein the mask patterns have junction regions or overlapping regions receiving double-exposures of electron beams which make widen or narrowed interconnection parts across the junction regions or overlapping regions, and wherein the method avoids a checker from discontinuing current checking operation even if double-exposed interconnection parts of the mask patterns are beyond the acceptable range or the upper limit.
It is a still further object of the present invention to provide a novel method of preparing checking data to be used for checking mask patterns free from the above problems.
It is yet a further object of the present invention to provide a novel method of preparing checking data to be used for checking mask patterns, wherein the mask patterns ha
Do Thuan
NEC Corporation
Smith Matthew
Young & Thompson
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