Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-01-30
2004-12-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C714S730000
Reexamination Certificate
active
06836440
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for checking the functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. The memory addresses of the chip can be selected by address lines electrically biased in a specific manner.
Methods of this type are used in the event of failure of individual memory chips on a memory module, for example a dual inline memory module (DIMM), in order to locate the cause of the failure. Usually responsible for the failure of a memory chip which cannot be properly read from or written to are ruptured soldered connections between the memory chip and the printed circuit board of the memory module.
Until now, the cause has been traced by visual inspection of the existing soldered joints of the address pin contacts. Alternatively, pin contacts selected on a sample basis and suspected of having a ruptured contact connection to the assigned address line of the printed circuit board are re-soldered.
Both methods are time-consuming and only conditionally reliable.
In principle, interrupted electrical connections between the address lines of the printed circuit board and the address line contacts of a semiconductor memory chip can also be traced electrically, in that voltage drops under a constant current are measured or currents under applied voltages are measured. In the case of memory modules with a number of memory chips, for example 8 or 16, the address line contacts of which are connected in parallel by the connected address lines, such tests do not work. Since each address line is connected to each of the memory chips via a pin contact, the created test circuit is closed even when the contact to one of the memory chips is interrupted, by the functioning contact connections to the other memory chips, whereby faultless functioning is indicated in spite of ruptured solder contacts.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of checking electrical connections between a memory module and a semiconductor memory chip that overcomes the above-mentioned disadvantages of the prior art methods of this general type, which is more reliable and less time-consuming and which works irrespective of the number of semiconductor chips mounted on the printed circuit board.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for checking a functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. Memory cells of the integrated semiconductor memory chip being selected by the address lines being electrically biased in a specific manner. The method includes checking the functional capability of the electrical connections by accessing the integrated semiconductor memory chip through writing and reading operations. The accessing step includes the steps of:
a) writing a first item of information to a first memory cell selected by none of the address lines being electrically biased;
b) writing a second item of information differing from the first item of information to a second memory cell selected by electrically biasing only a single address line;
c) reading from the integrated semiconductor memory chip with the first memory cell being selected by none of the address lines being electrically biased; and
d) checking whether the first item of information or the second item of information was read out.
A sequence of the steps a) to d) is then repeated a number of times and, with each repetition of the sequence of the steps a) to d), a different one of the address lines being electrically biased as the single address line during step b).
According to the invention, a specifically constructed memory test is used instead of an electrical resistance measurement to identify interrupted soldered connections. The invention is based on considerations as to how a semiconductor chip with partly damaged solder contacts reacts when writing and reading operations are initiated. In the case of defective solder contacts, they do not produce usable results in normal memory operation, but are used according to the invention to identify interrupted contact connections.
In a memory module, the memory addresses (cells) of a semiconductor memory chip are selected via address lines which can be electrically biased individually, independently of one another, and as a result, route a binary-coded address to that memory cell which is to be selected in a writing or reading operation. The address lines are connected to pin contacts of the semiconductor memory chip, which has in addition further pin contacts for control lines, data lines or clock lines. The data lines are used for transporting the data to be stored or to be read; the control lines and clock lines serve for making the memory chip operate properly. The address lines are used for transmitting the memory addresses into which the items of memory information transmitted by the data lines are written or from which they are read.
The invention is based in particular on the idea that, if one or more solder contacts are damaged, even though the memory address to be selected is no longer selected, a different memory address is accessed instead. The invention makes use of the fact that, in the event of a defective solder contact, an electrical biasing voltage that is applied to the address line concerned cannot be passed on. Since the electrical potential of the assigned pin contact of the memory chip is “floating”, the semiconductor chip registers with great probability a grounded address line, whereby, in conjunction with the voltage values of the remaining address lines, a different memory address than the one desired is selected. In normal memory operation, this perception is of no further assistance, since it is unknown which of the usually 14 address line contacts is defective.
According to the invention, however, use is made of the fact that in the semiconductor memory chip there is a single memory address which is always selected if the solder contacts of all the address lines or at least of all the electrically biased address lines are interrupted. The binary digit of this memory address is exclusively made up of “0” digital bits. Access to this memory address is used according to the invention to test the contact of a specific address line.
According to the invention, in step a), a first item of information, for example a digital “1”, is written into the memory address by none of the address lines being electrically biased. This makes use of the fact that, in the event of interrupted solder contacts, the corresponding contact pins of the memory chip are at a floating potential and consequently are with great probability grounded, so that even in the event of defective solder contacts precisely this memory address is selected. In step b), a different second item of information, for example a digital “0”, is written, the memory address now to be selected being selected by only a single address line being electrically biased. Subsequently, in step c), the first memory address is again selected and read from. In step d), it is checked whether this involved reading the item of information stored in step a) or the item of information stored in step b).
If the address line contact to be checked is working, in step b) the different second item of information is written into a different memory address than in step a). In step c), the first item of information stored in step a) is then read out again. If the contact to be checked is interrupted, however, in step b) the second memory address to be selected cannot be selected. Instead of this, since the pin contact does not register an electrical biasing voltage, the second item of information is likewise written into the first memory add
Adler Frank
Huber Thomas
Moser Manfred
Elms Richard
Greenberg Laurence A.
Hur J. H.
Infineon - Technologies AG
Mayback Gregory L.
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