Data processing: measuring – calibrating – or testing – Measurement system – Dimensional determination
Reexamination Certificate
2001-05-31
2004-11-09
Bui, Bryan (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Dimensional determination
C702S150000, C438S014000
Reexamination Certificate
active
06816806
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally directed to the field of semiconductor manufacture and, more particularly, to a method of making accurate, reliable and reproducible semiconductor surface characterization measurements, including identifying surface anomalies such as dishing and erosion regions, notwithstanding the presence of noise signals in the surface characterization map.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, there is an ever-present need for methods to further improve reliability, yield and cost.
Semiconductor manufacturing processes includes the steps of, for example, etching a plurality of spaced-apart trenches into a surface layer of a conventional dielectric material such as a silicon-based wafer. Once the trenches are formed, the process typically includes applying or plating, on the surface layer, a layer of an electrically-conductive metal such as copper, which also fills the trenches. The trench-filled and metal-covered surface of the dielectric wafer is subsequently polished, typically by a conventional process known in the art which employs a known form of chemical mechanical polish, down to the dielectric layer.
The dielectric layer, typically an oxide, is not as easily polished away during the chemical mechanical polishing process as the surface-deposited, trench-filling metal, principally because the metal is “softer” than the oxide. As a result, the oxide surface tends to serve as a mechanical “stop” during the chemical mechanical polishing process. Metal remaining in the trenches thus forms a pattern of conducting paths. Note that the term “dielectric,” as used herein, is to be understood to mean a substance which contains few or no free electrons and which has an electrical conductivity that is so low as to be considered an insulator.
One problem encountered in the above-described semiconductor manufacturing process is known as “dishing,” which occurs when a pad, used in the chemical mechanical polishing process, deforms into the metal-filled trench as a result of pressure applied by the pad in conjunction with the resistance presented by the oxide surface. As is appreciated by those skilled in the art, the depth of dishing into a trench may be deeper for wider trenches. Notably, anything other than minimal dishing is generally undesirable, since the result may adversely affect the desired electrical properties and/or functions of the metal deposited in the trench.
Another problem that may be encountered in conventional semiconductor manufacturing processes is “erosion” which occurs when a pad, used in the chemical mechanical polishing process, wears away some of the oxide surface as a result of the pressure applied by the pad opposite the oxide surface. It can be well appreciated that erosion is particularly undesirable for multiple alternating layers (along the semiconductor surface) of metal and dielectric material, as erosion of the dielectric material increases the risk of a short between adjacent metal layers. Thus, erosion is particularly problematic in semiconductor wafer structures having a relatively high number of tightly-packed metal-filled trenches with relatively thin walls of dielectric oxide wafer material between adjacent metal-filled trenches.
Similarly, in the event that the trench filling metal is harder than the oxide, the “eroded area” can actually rise above the oxide surface, according to a phenomenon known as “negative erosion.” More particularly, in this case, the polishing process removes the oxide faster than the metal due to the metal being generally harder, causing dishing in the oxide and the removal of the substrate “surface area” (see, for example,
18
in
FIG. 3
, discussed below) faster than the alternating metal layers, thus compromising the desired planarity of the resulting semiconductor surface.
Overall, erosion in conjunction with dishing may further adversely affect desired electrical properties and/or functions of the metal deposited in the trenches. In general, it is desirable for a semiconductor manufacturer to know when dishing and/or erosion is occurring, as well as the rate and amount of such dishing and/or erosion. Accuracy and precision, when locating the semiconductor upper surface as well as the bottom of dips due to dishing and erosion, must be statistically satisfactory, reliable and reproducible. Conventional methods are not.
A problem introduced when attempting to characterize the dishing and erosion phenomena is “noise.” Noise problems occur, for example, when dust and other air-borne and/or electrically-charged particles adhere to the semiconductor surface. In the context of the preferred embodiment, the “noise”-based problem affects the accuracy and efficiency of the dishing and/or erosion measurements. For example, while the noise-causing particles are often microscopic, it is important that a typical surface scan profile may include a total distance of about 2-5 millimeters along the semiconductor surface, involving perhaps 200-250 thousand points or “areas” of interest (or “regions”), wherein a vertical depth measurement for “dishing” purposes may be about 150-200 nanometers, and a typical vertical depth measurement for “erosion” purposes may be about 30-40 nanometers, wherein both depth measurements are made relative to the semiconductor surface.
One current method of profiling and characterizing a semiconductor surface after the chemical mechanical polishing procedure, includes scanning across a sample surface of the semiconductor with a conventional metrology instrument, and then generating a plot or map of the data. Such plots are typically presented to a semiconductor-manufacturing operator for analysis.
Conventional statistical averaging of the data, which attempts to correct for any noise that may be present, has not yet resulted in statistically satisfactory accuracy and precision, nor the attendant reliability and reproducibility of the semiconductor characterization information that is currently being sought by many semiconductor manufacturers. One such method averages the metrology data, including the noise signals, in an attempt to accurately determine the peaks. The averaging method is unreliable because it introduces error when noise signals are averaged.
Another method involves utilizing percentiles of the measurement data, including noise signals, in an attempt to determine peaks corresponding to dishing and erosion regions. The percentile method, unreliable because, like the averaging method, the noise signals must be accounted for when determining surface anomaly information, is not readily reproducible for the reason that an operator must exercise judgment regarding what percentile value to set any particular reading. The operator typically selects a level above or below which a certain percentage of the surface characterization points occur. For example, if the operator selects a particular depth, the percentile method may determine that 95% of the points are above that depth, thus indicating an extreme depth. However, in this example, the issue becomes whether the “95% level” corresponds to the low peak, indicating that the other 5% of the points may correspond to, for example, noise, or whether the level should be set lower to “catch” the peak. Clearly, this involves some guess work on the part of the operator, and often times will require some quantifying of the noise present in the data.
In some known scanning operations, information is obtained, stored and analyzed regarding the top surface (or reference) of the sample surface as well as deviations (e.g., dishing and erosion data) therefrom and noise information is extracted.
FIG. 1
illustrates typical topography data resulting from a scan of a semiconductor sample, and in particular, dips and spikes due to noise. The topography, and thus the noise signal (N.S.), runs from left to right along the scan direction (S.D.), as shown. Several spikes (S
1
, S
2
, S
3
, S
4
) extend upwardly from the smaller noise signals, and dips (D
1
, D
2
, D
3
) extend downwardly. Noise affects determ
Boyle Fredrickson Newholm Stein & Gratz S.C.
Bui Bryan
Veeco Instruments Inc.
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