Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-06
2003-11-11
Kielin, Erik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S687000, C427S533000, C427S535000
Reexamination Certificate
active
06645858
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a copper metal wiring in a semiconductor device. More particularly, the invention relates to a method of manufacturing a copper metal wiring in a semiconductor device capable of increasing absorption sites of a chemical enhancer when copper is deposited to form a metal wiring through a chemically enhanced chemical vapor deposition (CECVD) method.
2. Background of the Invention
As the performance of next-generation semiconductor device increases, the size of a contact is reduced and the aspect ratio increases. Therefore, when a metal wiring is formed, a good contact filling property and a step coverage is required.
Presently, the manufacture of a metal wiring in a semiconductor device uses a method by which, after a titanium thin film (Ti) is deposited, aluminum (Al) is deposited thereon by a physical vapor deposition (PVD) method and a chemical vapor deposition (CVD) method, or tantalum (Ta) or tantalum nitride (TaN) thin film is formed as a diffusion prevention film by a PVD method and copper (Cu) is deposited by an electroplating method. This current methodology, however, has a problem when applied to next-generation high-performance semiconductor devices since aluminum is higher in resistance than copper. In the latter method, copper is limited in its filling property due to an abrupt reduction in the contact size and an increase in the aspect ratio. Further, the tantalum nitride film used as a diffusion prevention film for copper must be very thin, which increases the resistance relative to aluminum to which a diffusion prevention film is not applied. Thus, applying the copper wiring to the next-generation semiconductor device or using aluminum wiring and electroplating causes many problems. In order to solve these problems, study of a method by which a CVD method is employed upon deposition of the copper wiring has recently been emphasized. However, due to a lower deposition speed, this method has a limit in bulk filling.
Recently, a method by which a copper thin film is deposited by means of a metal organic chemical vapor deposition (MOCVD) method using a catalyst that includes iodine (I) has been studied. The MOCVD method using this catalyst is called a chemically enhanced chemical vapor deposition (CECVD) method. The chemical enhancer, e.g., iodine, heavily depends on the surface property of a diffusion barrier layer. Further, if the chemical enhancer is directly deposited on the diffusion barrier layer without deposition of a seed, the absorption property of the chemical enhancer is degraded. In other words, in case of an amorphous layer or a dense thin film which does not provide a site on which the diffusion barrier layer can be deposited in a stable manner, the chemical enhancer will rarely adhere to the diffusion barrier layer and the chemically enhanced effect will be diminished. Therefore, there is a problem that a filling property of a copper metal wiring will be degraded.
SUMMARY OF THE DISCLOSURE
A method of manufacturing a copper metal wiring in a semiconductor device is disclosed and comprises the steps of forming an interlayer insulating film on a substrate in which an underlying structure is formed; forming a damascene pattern; performing a cleaning process; forming a diffusion barrier layer on the entire structure in which the damascene pattern is formed; performing a plasma process for the entire structure in which the diffusion barrier layer is formed; performing a chemical pre-process using a chemical enhancer for the diffusion barrier layer for which the plasma process is performed; depositing copper on the entire structure so that the damascene pattern can be filled; and performing a chemical mechanical polish process so that the damascene pattern can be filled, thus forming a copper metal wiring only within the damascene pattern.
REFERENCES:
patent: 5767301 (1998-06-01), Senzaki et al.
patent: 6107192 (2000-08-01), Subrahmanyan et al.
patent: 6121140 (2000-09-01), Arena et al.
patent: 6143658 (2000-11-01), Donnelly et al.
patent: 6291343 (2001-09-01), Tseng et al.
patent: 6297147 (2001-10-01), Yang et al.
patent: 6365502 (2002-04-01), Paranjpe et al.
patent: 6436826 (2002-08-01), Pyo
patent: 6468907 (2002-10-01), Pyo
patent: 2001/0019891 (2001-09-01), Koh et al.
patent: 2002/0052110 (2002-05-01), Pyo
patent: WO 02/63666 (2002-08-01), None
Hwang et al. “Surfactant-assisted metallorganic CVD of (111)-oriented copper films with excellent surface smoothness” Electrochemical and Solid State Letters 3(3), Mar. 2000, pp. 138-140.*
Wolf, et al. Silicon Processing for the VLSI Era, vol. 1-Process Technology, 2nd ed., Lattice Press: Sunset Beach CA, 2000, pp. 799-801.
Kim Si Bum
Pyo Sung Gyu
Hyundai Electronics Industries Co.
Kielin Erik
Marshall & Gerstein & Borun LLP
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