Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-27
2002-11-05
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C378S108000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06477686
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a system and method for capacitance extraction of an integrated circuit design and more particularly to an improved system and method which utilizes extension shapes to more accurately calculate capacitance near corners.
2. Description of the Related Art
In the design of a very large scale integrated (VLSI) circuit, one process involves extracting the parasitic capacitance of the devices and wiring within the structure. Accurate extraction of 3-dimensional conductor shapes with field calculations is very time consuming due to the large number of interacting conductor surfaces. Therefore, various techniques are used to simplify the calculation of parasitic capacitances, while maintaining an acceptable level of accuracy. Many conventional extraction programs are available to calculate the parasitic capacitance of the devices as viewed from the top in a two-dimensional plane. Any capacitance originating on the vertical edges of wiring and structures within such a two-dimensional plane and leading to a horizontal or vertical surface on a different layer is referred to as a “fringe capacitance”. The invention resolves the difficulty of calculating the fringe capacitance when working in a two-dimensional model, especially when adjacent structures interfere with or “screen” the fringe capacitance.
Typically, conventional extraction programs provide a unique algorithm for fringe capacitance wherein, a value is multiplied by the linear edge length of a structure. Such an algorithm is acceptable for straight structures which do not have closely spaced neighboring structures. However, when the devices for wiring have corners or are closely spaced, the multiplication constant in the conventional algorithm must be adjusted in a customized manner to account for the corner or the closely spaced neighbor. Therefore, there is a need for an automated system which simplifies the calculation of fringe capacitance when performing capacitance extraction on an integrated circuit design.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for performing a capacitance extraction on an integrated circuit, that includes determining the parallel-plate capacitance between conductors on different levels within the integrated circuit, adding extension shapes around each of the conductors, allowing overlapping of the extension shapes and reducing the total extension shape area, distributing the overlapping extension shapes to the conductor nets involved, multiplying the remaining area of the extension shapes and the overlapping area each by properly chosen constants to produce a fringe capacitance; and summing the parallel-plate capacitance and the fringe capacitance.
The extension shape is a two-dimensional annular shape. The overlapping extension shapes reduce the fringe capacitance within a level of the integrated circuit. The constant is based on a parallel-plate capacitance between each of the extension shapes and an extension shape or device in another level of the integrated circuit. The extension shapes are imaginary items added to the integrated circuit for the purpose of the capacitance extraction only and are not included in the finally manufactured product.
REFERENCES:
patent: 6185722 (2001-02-01), Darden et al.
patent: 6404851 (2002-06-01), Possin et al.
patent: 6405350 (2002-06-01), Tawada
Dewey, III L. William
Habitz Peter A.
Do Thuan
Kotulak, Esq. Richard M.
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