Method of bypassing a plurality of clock trees in EDA tools

Details Method of bypassing a plurality of clock trees in EDA tools Method of bypassing a plurality of clock trees in EDA tools

2005-04-26

2005-04-26

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06886146

ABSTRACT:
A method for using timing simulation and authentication software of an EDA tool (electronics design automatic tool) to bypass a plurality of clock trees in the EDA tool. The EDA tool contains a plurality of clocking devices that prevent the timing simulation and authentication software from changing an order of the plurality of clocking devices. The method includes measuring a delay time of the clocking device, and providing a first buffer, which is electrically connected to the clocking device, according to the delay time, wherein the delay time of the first buffer approximates the delay time of the clocking device.

REFERENCES:
patent: 5410491 (1995-04-01), Minami
patent: 6640277 (2003-10-01), Moertl

Affiliated with

Also associated with

Rating

Method of bypassing a plurality of clock trees in EDA tools does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of bypassing a plurality of clock trees in EDA tools, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of bypassing a plurality of clock trees in EDA tools will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3414299