Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-11-29
2003-07-01
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06586313
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a method for fabricating integrated circuits (IC) comprising non-volatile memory cell matrices and peripheral circuits.
2. Description of the Related Art
A well-known method for device isolation in an IC is the so-called Local Oxidation of Silicon (LOCOS) technique. According to this technique inserts of silicon dioxide (field oxide) are formed in a silicon substrate to provide electrical isolation between components of the IC. As integration becomes higher, this technique can hardly be used because of certain inherent limitations of the resulting isolation structure, such as the so called “bird's beak” formation.
In sub-half micron semiconductor fabrication is now widely used another isolation technique, known as Shallow Trench Isolation (STI).
A conventional method for fabricating an STI structure is described in the following with reference to
FIGS. 1A-1F
, which show sectional views of a portion of a silicon wafer in the initial steps of the fabrication of an IC.
Referring first to
FIG. 1A
, a silicon substrate
10
is prepared and thermally oxidized to grow a layer
11
of silicon dioxide. Next, a layer
12
of silicon nitride is formed over the oxide layer
11
, a photoresist layer
13
is laid on the nitride layer
12
and selectively removed to serve as an etching mask. Then, an anisotropic etching is performed to remove the unmasked portions of the nitride layer
12
with the underlying oxide
11
and to etch the substrate
10
until a predetermined depth (typically 270-300 nm), to form a plurality of trenches
14
. After this, the rest of the photoresist layer
13
is removed.
Referring next to
FIG. 1B
, silicon dioxide is deposited, for example by an atmospheric-pressure chemical vapor deposition (APCVD) process, into the trenches
14
and over the silicon nitride layer
12
to form a silicon dioxide layer
16
. The oxide layer
16
is then densified by heating the wafer at a temperature of about 1,000° C. for 10 to 30 minutes. Usually, before the APCVD step a thermal oxidation is performed to grow a thin layer of silicon dioxide on the surfaces of the trenches
14
. To simplify the drawing this thin layer is not shown in the figures.
Referring to
FIG. 1C
, a Chemical-Mechanical Polishing (CMP) is performed to remove the upper portion of the oxide layer
16
using the nitride layer
12
as a stop layer. The portions of oxide layers
16
lying in the trenches
14
, usually referred to as “plugs”, are indicated by the same reference numeral
16
.
Referring to
FIG. 1D
the nitride layer
12
and the oxide layer
11
are removed by using suitable etchants. During the step for removing the oxide layer
11
, the plugs
16
are also etched and are leveled substantially to the top surface of the substrate
10
. The resulting STI structure is formed as shown with recesses
17
in the oxide near the edges of the trenches. This is because the etching solution, usually HF, used to remove the oxide layer
11
etches the plug oxide, which is deposited silicon dioxide, more rapidly than the thermal silicon dioxide of layer
11
and because the plug oxide extends to a level higher than the level of oxide layer
11
.
At this stage, different process steps are required to form a matrix of cells for the non-volatile memory, such as a flash memory, and peripheral circuits, i.e. circuits for driving the memory and other circuits, such as logic processing circuits. First, layers of different materials required for the memory matrix are successively formed on the entire substrate, then the substrate areas intended for the matrix are covered by a mask and the portions of these layers not covered by the mask and intended for the peripheral circuits are entirely removed to enable subsequent steps for the formation of components of the peripheral circuits. In particular, as shown in
FIG. 1E
, where a section of a substrate portion intended for the peripheral circuits is shown, a “tunnel” oxide layer
20
, i.e. a thin oxide layer, to be used for the “tunnel” dielectric in the memory cells, is grown by thermal oxidation of the silicon substrate
10
. Typically, the tunnel oxide has a thickness of 10-11 nm. Then a “floating gate” polysilicon layer or poly-
1
layer
21
, i.e. a layer of doped polysilicon to be used for the floating gates of the memory cells, is deposited over the “tunnel” oxide layer
20
. Next, an “interpoly” oxide layer
22
, i.e. a dielectric layer, or several superimposed layers, usually silicon Oxide, silicon Nitride and silicon Oxide (ONO), to be used for insulating the floating gates of the matrix cells from the control gates obtained from another polysilicon layer to be formed in a following step, is deposited over the poly-
1
layer
21
. A photoresist layer
23
is deposited and selectively removed to serve as a mask for protecting the areas, not shown, intended for the memory matrix. The portions of layers
22
,
21
and
20
overlying the areas intended for the peripheral circuits are then removed. In particular, the interpoly dielectric layer
22
and the poly-
1
layer
21
are removed by a dry etching step and the tunnel oxide layer
21
is removed by using a Buffered Oxide Etching (BOE) solution. The time for the wet BOE etching step is determined in accordance with the thickness of the tunnel oxide layer
20
.
The photoresist mask is then entirely removed and the usual steps for forming the memory cells and the components of the peripheral circuits are performed, in particular
depositing a doped polysilicon layer, or poly-
2
, intended for forming the control gates of the memory cells,
defining the matrix array by a self-aligned etching,
forming source and drain regions for the memory cells—and transistors of the peripheral circuits,
removing the exposed tunnel oxide (optional),
defining poly-
2
pattern for interconnections in the peripheral circuits,
etching oxide for a Self-Aligned Source (SAS) formation,
reoxidation for sealing the memory matrix,
defining spacers,
“pre-metal” deposition,
contact opening and metal deposition and definition.
Wafers processed according to the method described above have a relatively low yield because of a high concentration of defective devices in the border zones of the wafer.
BRIEF SUMMARY OF THE INVENTION
In view of the state of the art described, an embodiment of the present invention provides a method which is able to increase the production yield.
The invention is based on the hypothesis that the observed concentration of defective devices in the border zones of the wafer is directly related with the CMP steps. More particularly, it is supposed that the recesses formed in the isolation plugs near the edges of the trenches, as indicated at
17
in
FIG. 1D
, may remain filled with doped polysilicon deposited in process steps following the STI process, thus causing short-circuits between adjacent components. It is also supposed that this problem affects more the peripheral circuits, where the active areas have different sizes, than the memory matrix, where the active areas have all the same size.
The improved method applies to the fabrication of integrated circuits comprising non-volatile memory devices and peripheral circuits.
A preferred embodiment of this method comprises the steps of preparing a silicon substrate, carrying out a shallow trench isolation (STI) process on the silicon substrate to obtain active areas of exposed silicon isolated from one another by trenches filled with field oxide, growing a thin oxide layer on the active areas, depositing a first layer of a conductive material, depositing a second layer of an insulating material, masking the substrate areas intended for the memory cell matrices, removing the insulating material of said second layer and the conductive material of said first layer from the unmasked areas to expose the thin oxide layer and the field oxide of the substrate areas intended for the peripheral circuits and etching the thin oxide layer and the field oxide by a chemical etch for a time
Blum David S
de Guzman Dennis M.
Jorgenson Lisa K.
Jr. Carl Whitehead
Seed IP Law Group PLLC
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