Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-06-27
2004-10-12
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S700000
Reexamination Certificate
active
06803307
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present application relates to methods of fabricating integrated circuit devices and, more particularly, to methods of fabricating contact holes with spacers having an improved top critical dimension.
2. Description of Related Art
An important capability for manufacturing reliable integrated circuits is to precisely shape the individual structures that form the integrated circuits. One such structure is a contact hole. Conducting material may be deposited into a formed contact hole to provide a vertical electrical pathway between horizontal layers within an integrated circuit. Integrated circuits may comprise multiple layers, and contact holes are implemented between each layer to allow electrical communication between neighboring layers. Conventional integrated circuits may require millions of contact holes with a precise uniform diameter or critical dimension (CD).
The prior art can have problems creating a contact hole having a uniform CD from top to bottom. Typical prior art methods for manufacturing a contact hole tend to produce a contact hole that increases in diameter near the top of the contact hole. This increase in the CD near the top of the contact hole can diminish the reliability of the integrated circuit.
A prior art manufacturing process for creating a contact hole with a spacer is elucidated in
FIG. 1
a,
wherein a substrate
100
is depicted covered by a first dielectric layer
102
. The substrate
100
may comprise a silicon wafer and the first dielectric layer
102
may comprise a deposited silicon dioxide layer. The first dielectric layer
102
may be used, as is known in the art, as an interlayer dielectric (ILD) layer. A patterned photoresist layer
104
having an opening
104
a
may be formed on the first dielectric layer
102
using conventional techniques.
FIG. 1
b
illustrates a portion of the integrated circuit illustrated in
FIG. 1
a
after the first dielectric layer
102
has been etched using the patterned photoresist
104
as a mask to form a contact hole
102
a.
A timed or controlled etching process may be implemented alone or in combination with an etchant that is selective toward the dielectric layer
102
in relation to the substrate
100
, to thereby deter etching into the substrate
100
as the contact hole
102
a
exposes the upper surface of the substrate
100
. In
FIG. 1
c,
a conformal second dielectric layer
106
is formed on the first dielectric layer
102
and in the contact hole
102
a.
The conformal second dielectric layer
106
may be a deposited silicon oxide or tetraethylorthosilicate (TEOS) oxide layer. The conformal second dielectric layer may be deposited using either a physical or chemical vapor deposition process.
In
FIG. 1
d,
the second dielectric layer
106
is anisotropically etched away to leave a spacer
106
b
on the sidewall of the contact hole
106
a
. The CD of the contact hole
106
a
depends in part on the uniformity of the thickness of the spacer
106
b
and shape of the first dielectric layer
102
. However, the upper surface of the first dielectric layer
102
is typically over-etched during the anisotropic etching process used to form the spacer
106
b
in the contact hole
106
a
. The CD of the upper portion of the contact hole
106
a
is thus enlarged as a consequence of the upper edge of the contact hole
106
a
being substantially rounded. As a result of the nonuniform CD of the contact hole
106
a
, the reliability of the integrated circuit can be attenuated.
To continue to meet demands for increasing the reliability of integrated circuits, new methods are needed to overcome the limitations of current methods. Thus, there remains a need for methods of fabricating integrated circuit devices which reduces or eliminates the problems associated with conventional methods, including, for example, the problems associated with manufacturing contact holes having a uniform CD.
SUMMARY OF THE INVENTION
The present invention addresses these needs by providing methods of fabricating contact holes with spacers through interlayer dielectric layers wherein the CD of the contact holes remains relatively uniform from top to bottom. Specifically, an object of the invention is to provide manufacturing methods for contact holes with spacers that serve to prevent the CD of the upper portions of the contact holes from becoming substantially enlarged.
In accordance with the present invention, an exemplary method for making a contact hole with a spacer comprises a step of forming a first dielectric layer on a substrate, followed by a step of forming an etch stop, such as a dielectric antireflective coating layer, over the first dielectric layer. In a preferred embodiment, the first dielectric layer comprises silicon oxide and the substrate is a semiconductor wafer. The first dielectric layer may be deposited, as is known in the art, by physical or chemical vapor deposition. The antireflective coating layer, which can comprise, for example, SiON (silicon oxynitride), may then be formed over the first dielectric layer using a deposition process.
A photoresist layer may then be formed on the antireflective coating layer and patterned using known photolithographic techniques. Using the patterned photoresist layer as a template, an etching process may then be used to etch contact holes into the antireflection coating layer and the first dielectric layer. The contact holes are advantageously of sufficient depth to expose a surface of the underlying substrate. The etching process should have a relatively low selectivity toward the substrate to prevent dishing or excessive etching of the upper surface of the substrate. The photoresist may then be removed and the substrate cleaned.
A conformal second dielectric layer comprising a material, such as silicon oxide, may be formed over the antireflective coating layer and into the contact holes. The conformal second dielectric layer may be anisotropically etched, preferably with a process having a relatively low etching selectivity with the antireflective coating layer and with the substrate. The process removes the second dielectric layer over the antireflective coating layer while leaving the second dielectric layer on the wall of the contact holes, thereby forming spacers within the contact holes. Conductive material may now be deposited into the contact holes to provide a vertical electrical path between the substrate and an interconnect layer that will be created over the contact holes.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.
REFERENCES:
patent: 5496765 (1996-03-01), Schwalke
patent: 6096594 (2000-08-01), Lin et al.
patent: 2002/0110992 (2002-08-01), Ho
Le Dung A.
Macronix International Co. Ltd.
Stout, Uxa Buyan & Mullins, LLP
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