Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-16
2008-05-13
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07373628
ABSTRACT:
A technique will automatically route interconnect of an integrated circuit. In an implementation, the technique operates on a gridless layout. The technique forms a Steiner tree for a net and routs using the Steiner tree. In a specific embodiment, the technique creates tracks having varying widths.
REFERENCES:
patent: 4615011 (1986-09-01), Linsker
patent: 4673966 (1987-06-01), Shimoyama
patent: 4777606 (1988-10-01), Fournier
patent: 4782193 (1988-11-01), Linsker
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 4855253 (1989-08-01), Weber
patent: 4965739 (1990-10-01), Ng et al.
patent: 5072402 (1991-12-01), Ashtaputre et al.
patent: 5272645 (1993-12-01), Kawakami et al.
patent: 5353235 (1994-10-01), Do et al.
patent: 5375069 (1994-12-01), Satoh et al.
patent: 5500804 (1996-03-01), Honsinger et al.
patent: 5541005 (1996-07-01), Bezama et al.
patent: 5550748 (1996-08-01), Xiong
patent: 5635736 (1997-06-01), Funaki et al.
patent: 5636129 (1997-06-01), Her
patent: 5637920 (1997-06-01), Loo
patent: 5640327 (1997-06-01), Ting
patent: 5646830 (1997-07-01), Nagano
patent: 5650653 (1997-07-01), Rostoker et al.
patent: 5689433 (1997-11-01), Edwards
patent: 5723908 (1998-03-01), Fuchida et al.
patent: 5757089 (1998-05-01), Ishizuka
patent: 5784289 (1998-07-01), Wang
patent: 5801385 (1998-09-01), Endo et al.
patent: 5801959 (1998-09-01), Ding et al.
patent: 5811863 (1998-09-01), Rostoker et al.
patent: 5822214 (1998-10-01), Rostoker et al.
patent: 5880969 (1999-03-01), Hama et al.
patent: 5889329 (1999-03-01), Rostoker et al.
patent: 5980093 (1999-11-01), Jones et al.
patent: 6111756 (2000-08-01), Moresco
patent: 6150193 (2000-11-01), Glenn
patent: 6219823 (2001-04-01), Hama et al.
patent: 6260183 (2001-07-01), Raspopovic et al.
patent: 6262487 (2001-07-01), Igarashi et al.
patent: 6263475 (2001-07-01), Toyonaga et al.
patent: 6279142 (2001-08-01), Bowen et al.
patent: 6282693 (2001-08-01), Naylor et al.
patent: 6295634 (2001-09-01), Matsumoto
patent: 6301686 (2001-10-01), Kikuchi et al.
patent: 6301693 (2001-10-01), Naylor et al.
patent: 6307256 (2001-10-01), Chiang et al.
patent: 6316838 (2001-11-01), Ozawa et al.
patent: 6323097 (2001-11-01), Wu et al.
patent: 6324674 (2001-11-01), Andreev et al.
patent: 6324675 (2001-11-01), Dutta et al.
patent: 6349403 (2002-02-01), Dutta et al.
patent: 6408427 (2002-06-01), Cong et al.
patent: 6412097 (2002-06-01), Kikuchi et al.
patent: 6442745 (2002-08-01), Arunachalam et al.
patent: 6448591 (2002-09-01), Juengling
patent: 6480993 (2002-11-01), Suto et al.
patent: 6480996 (2002-11-01), Aji et al.
patent: 6507941 (2003-01-01), Leung et al.
patent: 6510545 (2003-01-01), Yee et al.
patent: 6516455 (2003-02-01), Teig et al.
patent: 6526555 (2003-02-01), Teig et al.
patent: 6543043 (2003-04-01), Wang et al.
patent: 6564366 (2003-05-01), Marchenko et al.
patent: 6598215 (2003-07-01), Das et al.
patent: 6645842 (2003-11-01), Igarashi et al.
patent: 6662348 (2003-12-01), Naylor et al.
patent: 6671859 (2003-12-01), Naylor et al.
patent: 6711727 (2004-03-01), Teig et al.
patent: 6734472 (2004-05-01), Ho
patent: 6895567 (2005-05-01), Teig et al.
patent: 6928401 (2005-08-01), Wanek
patent: 7065729 (2006-06-01), Chapman
patent: 2001/0004763 (2001-06-01), Kato
patent: 2001/0009031 (2001-07-01), Nitta et al.
patent: 2002/0069397 (2002-06-01), Teig et al.
patent: 2003/0018401 (2003-01-01), Sorkin
patent: 2003/0025205 (2003-02-01), Shively
patent: 2005/0240893 (2005-10-01), Teig et al.
patent: 03262144 (1991-11-01), None
NB83123895, “Wiring Multinode Nets”, IBM Technical Disclosure Bulletin, vol. 26, No. 7B, Dec. 1983, pp. 3895-3900 (6 pages).
Moulton, “Laying the Power and Ground Wires on a VLSI Chip”, 20th Conference on Design Automation, Jun. 27-29, 1983, pp. 754-755.
Strobandt, “A Priori Wire Length Distribution Models With Multiterminal Nets”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 1, Feb. 2003, pp. 35-43.
Finch, “A Method for Gridless Routing of Printed Circuit Boards”, Paper 32.2, 22nd Design Automation Conference, IEEE, 1985, pp. 509-515, Racal-Redac Ltd., Newtown, Tewkesbury, Glos, United Kingdom.
Ng, “A ‘Gridless’ Variable-Width Channel Router for Macro Cell Design”, 24th Conference on Design Automation, May 28-Jun. 1, 1987, pp. 633-636.
Dubois et al., “New Advances in the Routing of Mixed Analog and Digital Channels”, IEEE International Symposium on Circuits and Systems, vol. 4, Jun. 11-14, 1991, pp. 1956-1959.
Polk, “A Three-Layer Gridless Channel Router with Compaction”, 24th Conference on Design Automation, May 28-Jun. 1, 1987, pp. 146-151.
Chen et al., “Glitter: A Gridless Variable-Width Channel Router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 5, No. 4, pp. 459-465.
Balsdon Graham
Birch Jeremy
Parker Tim
Sato Fumiaki
Waller Mark
Aka Chan LLP
Kik Phallaka
Pulsic Limited
LandOfFree
Method of automatically routing nets using a Steiner tree does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of automatically routing nets using a Steiner tree, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of automatically routing nets using a Steiner tree will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3987720