Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-14
2007-08-14
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10908895
ABSTRACT:
A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.
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Balsdon Graham
Birch Jeremy
Parker Tim
Sato Fumiaki
Waller Mark
Chan LLP Aka
Chiang Jack
Parihar Suchin
Pulsic Limited
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