Method of automated ESD protection level verification

Details Method of automated ESD protection level verification Method of automated ESD protection level verification

1998-01-29

2000-07-11

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

G06F 1750

Patent

active

060866276

ABSTRACT:
A integrated circuit (IC) chip with ESD protection level and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design and array pads are wired to I/O cells located on the chip. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection level. The design is then verified by first identifying the chip pads, I/O cells and ESD protect devices. Connections between these three structures are verified. Wires between the ESD protect devices and the chip pads and I/O cells are shrunk such that unsuitable connections becomes opens (disconnected) and are found in subsequent checking. Finally connections to guard rings are checked. Power rails are checked in a similar manner.

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