Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-25
2005-01-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06848095
ABSTRACT:
A method of assigning logic functions to macrocells assures that a maximum number of macrocells are assigned two or more logic functions. A first logic function is assigned to a macrocell without restriction. Rules are then applied to the macrocell to determine whether a second logic function may be assigned to the macrocell, and, if so, whether any restrictions exist on what the second logic function may be.
REFERENCES:
patent: 4871930 (1989-10-01), Wong et al.
patent: 5015884 (1991-05-01), Agrawal et al.
patent: 6229337 (2001-05-01), Xiao et al.
patent: 6255847 (2001-07-01), Chan et al.
patent: 6294925 (2001-09-01), Chan et al.
patent: 6531890 (2003-03-01), Agrawal et al.
“ispLSI® 5000V Family Architectural Description” published in Dec. 2001 by Lattice Semiconductor Corporation.
Dinh Paul
Lattice Semiconductor Corp.
Siek Vuthe
LandOfFree
Method of assigning logic functions to macrocells in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of assigning logic functions to macrocells in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of assigning logic functions to macrocells in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3393329